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high performance ism band fsk/ask transceiver ic prelim inary technical data adf7020 rev. pr h in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features low power, low if transceiver frequenc y ban d s: 433 mh z to 46 4 mhz 862 mh z to 92 8 mhz data rat e s sup p orted: 0.3 kbps to 200 kbps, fsk 0.3 kbps to 64 kbps, ask 2.3 v to 3.6 v p o wer supply programmable output power: ?16 dbm to +1 3 dbm in 0. 3 d b m steps receiver sensit ivity: ?117.5 dbm at 1 kbps, fsk ?110.5 dbm at 9.6 kbps, fsk ?106.5 dbm at 9.6 kbps, ask low power con s umption: 19 ma in receive mode 22 ma in trans m it mode (10 dbm output) on-chip v c o and fractional-n pll on-chip 7-bit adc and temper ature sensor 1 ppm rf out p ut freq uency accuracy possible from low cost 100 p p m crystal digital rssi leakage curre nt <1 a in power-down mode 48-lea d ultras mall mlf pack age (chip scale) applic ati o ns low cost wirel e ss dat a transf er remote control/security s y ste m s w i r e l e s s me t e ri n g keyless entry home automat i on process and building control wireless voice func tio n a l block di agram tx /r x co nt ro l ag c co n t ro l fs k / a s k de m o dul at o r dat a s y n ch ro ni z e r if f i l t e r r ssi 7- b i t adc ga i n di v r ser i a l po r t as k / o o k mo d c o n t r o l g a u ssi a n f i l t er p a ou t o f f set co rr e c t i o n o f f set co rr e c t i o n ln a vc o pf d cp af c co n t ro l osc di v i d e r s / mu xi n g n/ n+ 1 di v p mu x t emp sen so r ri ng os c cl k di v cl k out t est mu x vcoi n c po u t bi a s ld o( 1: 4 ) mu xo u t a d ci n r set vr e g (1 :4 ) r lna r fin rfinb sl e sd a t a i n ce rx cl k c l k out s d at a o ut sc l k in t / lo c k t x / r x dat a fs k m od co nt ro l g aus s i an fi l t e r - ? mo d u l a t o r 01975-p r g-001 fi g u r e 1 .
adf7020 preliminary technical data rev. prh | page 2 of 40 table of contents general description ......................................................................... 3 specifications ..................................................................................... 4 timing characteristics ..................................................................... 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 frequency synthesizer ................................................................... 11 reference input section ............................................................. 11 choosing channels for best system performance ................. 13 transmitter ...................................................................................... 14 modulation schemes .................................................................. 14 receiver section .............................................................................. 16 rf front end ............................................................................... 16 rssi/agc section ...................................................................... 17 fsk demodulators on the adf7020 ....................................... 17 fsk correlator/demodulator ................................................... 17 linear fsk demodulator .......................................................... 19 afc section ................................................................................ 19 automatic sync word recognition .......................................... 20 applications section ....................................................................... 21 lna/pa matching ...................................................................... 21 transmit protocol and coding considerations ..................... 22 image rejection calibration ..................................................... 22 device programming after initial power-up ......................... 22 serial interface ................................................................................ 24 readback format ........................................................................ 24 register 0n register ............................................................... 25 register 1oscillator/filter register ...................................... 26 register 2transmit modulation register (ask/ook mode) ........................................................................................... 27 register 2transmit modulation register (fsk mode) ..... 28 register 2transmit modulation register (gfsk/gook mode) ........................................................................................... 29 register 3receiver clock register ....................................... 30 register 4demodulator setup register ............................... 31 register 5sync byte register ................................................. 32 register 6correlator/demodulator register ...................... 33 register 7readback setup register ...................................... 34 register 8power-down test register .................................. 35 register 9agc register ......................................................... 36 register 10agc 2 register .................................................... 37 register 11afc register ....................................................... 37 register 12test register ......................................................... 38 register 13offset removal and signal gain register ....... 39 outline dimensions ....................................................................... 40 ordering guide .......................................................................... 40 revision history revision prh: preliminary version
preliminary technical data adf7020 rev. prh | page 3 of 40 general description the adf7020 is a low power, highly integrated fsk/gfsk/ ask/ook/gask transceiver designed for operation in the license-free ism bands at 433 mhz, 868 mhz, and 915 mhz. it is suitable for circuit applications that meet either the european etsi-300-220 or the north american fcc (part 15) regulatory standards. a complete transceiver can be built using a small number of external discrete components, making the adf7020 very suitable for price-sensitive and area-sensitive applications. the transmit section contains a vco and low noise fractional-n pll with output resolution of <1 ppm. the vco operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. the transmitter output power is programmable in 0.3 db steps from ?16 dbm to +13 dbm. the transceiver rf frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. the device operates with a power supply range of 2.3 v to 3.6 v and can be powered down when not in use. a low if architecture is used in the receiver (200 khz), minimizing power consumption and the external component count and avoiding interference problems at low frequencies. the adf7020 supports a wide variety of programmable features including rx linearity, sensitivity, and if bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. the receiver also features a patent-pending automatic frequency control (afc) loop, allowing the pll to track out the frequency error in the incoming signal. an on-chip adc provides readback of an integrated tempera- ture sensor, an external analog input, the battery voltage, or the rssi signal, which provides savings on an adc in some applications. the temperature sensor is accurate to 5c over the full operating temperature range of ?40c to +85c.
adf7020 preliminary technical data rev. prh | page 4 of 40 specifications v dd = 2.3 v to 3.6 v, gnd = 0 v, t a = t min to t max , unless otherwise noted. typical specifications are at v dd = 3 v, t a = 25c. all measurements are performed using the test circuit in figure tbd using pn9 data sequence, unless otherwise noted. table 1. paraeter min tp max nit test conditions rf characteristics frequency ranges 862 928 mhz frequency ranges (divide-by-2 mode) 433 464 mhz phase frequency detector frequency rf/256 20 mhz transmission parameters data rate fsk/gfsk 0.3 200 kbps data rate ook/ask 0.3 64 1 kbps frequency shift keying gfsk/fsk frequency deviation 2 , 3 1 110 khz pfd = 3.625 mhz 4.88 620 khz pfd = 20 mhz deviation frequency resolution 100 hz pfd = 3.625 mhz gaussian filter bt 0.5 adjacent channel power, gfsk tbd dbc channel spacing = 25 khz, measured in adjacent channel 8.5 khz from center; dr = 4.8 kbps, f dev = 2.4 khz, frf = 868 mhz ?50 dbc 868.95 mhz 250 khz, dr = 38.4 kbps, f dev = 19.2 khz amplitude shift keying ask modulation depth 30 db ook Cpa off feedthrough ?50 dbm transmit power 4 ?20 +13 dbm frf = 915 mhz, v dd = 3.0 v, t a = 25c tbd dbm frf = 868 mhz, v dd = 3.0 v, t a = 25c tbd dbm frf = 433 mhz, v dd = 3.0 v, t a = 25c transmit power variation highest power setting tbd dbm frf = 915 mhz, v dd = 3.6 v 13 dbm frf = 915 mhz, v dd = 3.0 v tbd dbm frf = 915 mhz, v dd = 2.3 v transmit power flatness tb d db from 902 mhz to 928 mhz programmable step size ?20 dbm to +13 dbm 0.3125 db spurious emissions during pll settling ?57 db m mute pa until lock enabled (r2_db5 =1 ) integer boundary ?55 dbc 50 khz loop bw reference ?65 dbc harmonics second harmonic ?27 ?18 dbc third harmonic ?21 ?18 dbc all other harmonics ?35 dbc vco frequency pulling, ook mod tbd khz rms dr = 9.6 kbps optimum pa load impedance 5 tbd ? frf = 915 mhz tbd ? frf = 868 mhz tbd ? frf = 433 mhz receiver parameters fsk input sensitivity 6 at ber = 1e ? 3, frf = 915 mhz high sensitivity mode ?117.5 dbm dr = 1 kbps, f dev = 5 khz low current mode ?tbd dbm dr = 1 kbps, f dev = 5 khz see notes at end of table.
preliminary technical data adf7020 rev. prh | page 5 of 40 parameter min typ max unit test conditions high sensitivity mode ?110.5 dbm dr = 9.6 kbps, fdev = 10 khz low current mode ?104 dbm dr = 9.6 kbps, fdev = 10 khz high sensitivity mode ?99 dbm dr = 200 kbps, fdev = 50 khz low current mode ?tbd dbm dr = 200 kbps, fdev = 50 khz ook input sensitivity at ber = 1e ? 3, frf = 915 mhz high sensitivity mode ?tbd dbm dr = 1 kbps low current mode ?tbd dbm dr = 1 kbps high sensitivity mode ?106.5 dbm dr = 9.6 kbps low current mode ?tbd dbm dr = 9.6 kbps lna and mixer input ip3 7 enhanced linearity mode 6.8 dbm pin = ?20 dbm, 2 cw interferers low current mode ?3.2 dbm frf = 915 mhz, f1 = frf + 3 mhz high sensitivity mode ?35 dbm f2 = frf + 6 mhz, maximum gain rx spurious emissions 8 ?57 dbm <1 ghz at antenna input ?47 dbm >1 ghz at antenna input afc pull-in range 50 khz if_bw = 200 khz response time tbd bits accuracy 1 tbd khz channel filtering adjacent channel rejection (offset = 1 if filter bw setting) 27 db second adjacent channel rejection (offset = 2 if filter bw setting) 50 db third adjacent channel rejection (offset = 3 if filter bw setting) tbd db if filter bw settings = 100 khz, 150 khz, 200 khz desired signal 3 db above the input sensitivity level, cw interferer power level increased until ber = 10 ?3 , image channel excluded image channel rejection 30 db uncalibrated (image channel = frf ? 400 khz) tbd db calibrated 9 co-channel rejection ?3 db wide-band interference rejection tbd db swept from 100 mhz to 2 ghz, measured as channel rejection saturation (maximum input level) 12 dbm fsk mode, ber = 10 ?3 input impedance tbd ? frf = 915 mhz, rfin, rfin to gnd tbd ? frf = 868 mhz tbd ? frf = 433 mhz rssi range at input ?100 to ?36 dbm linearity 3 db absolute accuracy tbd db response time 350 s maximum input step change, agc included, rssi ready for readback phase locked loop vco gain 65 mhz/v 902 mhz to 928 mhz band., vco adjust = 0 130 mhz/v 860mhz to 870 mhz band, vco adjust = 0 tbd mhz/v at 433mhz, vco adjust = 0 phase noise (in-band) ?92 dbc/hz pa = 0 dbm, v dd = 3.0 v, pfd = 10 mhz, frf = 915 mhz, vco bias = 4 phase noise (out-of-band) ?110 dbc/hz at 1 mhz offset residual fm tbd hz from 300 hz to 5 khz see notes at end of table.
adf7020 preliminary technical data rev. prh | page 6 of 40 parameter min typ max unit test conditions pll settling time 40 s measured for a 10 mhz frequency step to within 5 ppm accuracy, pfd = 20 mhz, lbw = tbd reference input crystal reference 3.625 24 mhz external oscillator 3.625 24 mhz load capacitance tbd pf input level cmos levels see the reference input section timing information chip enabled to regula tor ready tbd s c reg = 100 nf crystal oscillator startup time 1 ms with 19.2 mhz xtal tx to rx turnaround time 350 s + (5 t bit ) time to synchronized data, includes agc settling logic inputs v inh, input high voltage 0.7 v dd v v inl , input low voltage 0.2 v dd v i inh /i inl, input current 1 a c in , input capacitance 10 pf control clock input 50 mhz logic outputs v oh ,output high voltage dv dd ? 0.4 v i oh = 500 a v ol , output low voltage 0.4 v i ol = 500 a clk out rise/fall 5 ns clk out load 10 pf temperature ranget a ?40 +85 c power supplies voltage supply av dd 2.3 3.6 v dv dd av dd av dd transmit current consumption frf = 915 mhz, v dd = 3.0 v, pa is matched in to 50 ? ?20 dbm tbd ma ?10 dbm 12 ma vco_bias_setting = 3 0 dbm 15 ma 10 dbm 22 ma receive current consumption low current mode 19 tbd ma high sensitivity mode 21 tbd ma power-down mode low power sleep mode 0.1 1 a 1 higher data rates are achievable depending on local regulations. 2 for definition of frequency deviation, see the r section. egister 2transmit modulation register (fsk mode) 3 for definition of gfsk frequency deviation, see the r section. egister 2transmit modulation register (gfsk/gook mode) 4 measured as maximum unmodulated power. output power varies with both supply and temperature. 5 for matching details, see the ln section. a/pa matching 6 see table 5 for description of different receiver modes. 7 see table 5 for description of different receiver modes. 8 follow the matching and layout guidelines to achieve the relevant fcc/etsi specifications. 9 see the section. image rejectio n calibration
prelim inary technical data adf7020 r e v. pr h | pa g e 7 of 40 timing characteristics v dd = 3 v 10%; v g nd = 0 v , t a = 2 5 c , u n l e ss ot he r w i s e not e d. gu a r a n t e e d by d e s i g n , bu t n o t pro d u c t i on t e s t e d . table 2. paraeter liit at t min to t ma n i t t e s t condition s / c o e n t s t 1 <10 ns sdata to sclk setup time t 2 <10 ns sdata to sclk hold time t 3 <25 ns sclk high dura tion t 4 <25 ns sclk low duration t 5 <10 ns sclk to sle set u p time t 6 <20 ns sle pulse width t 7 adf7020 prelim inary technical data r e v. pr h | pa g e 8 of 40 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a e t e r a t i n v dd to gnd 1 ?0.3 v to +5 v analog i/o voltage to gnd ?0.3 v to av dd + 0.3 v digital i/o voltage to gnd ?0.3 v to dv dd + 0.3 v operating tem p erature range indus t rial (b vers io n) ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature 125c mlf ja thermal impedance tbdc/w lead temperature soldering vapor phase (60 s) 235c infrared (15 s) 240c 1 gnd = cp gnd = r f gnd = dgnd = agnd = 0 v. s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y a nd f u n c t i o n al op era t io n o f t h e de v i ce a t t h es e o r a n y o t h e r con d i t io n s ab o v e t h o s e i n dica t e d in t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . this de vice is a hig h -p er f o r m a n ce rf in t e g r a t e d cir c ui t wi t h an es d ra tin g o f <2 kv and i t is e s d s e n s i t i v e . p r o p er p r eca u tio n s s h o u ld b e ta k e n f o r ha n d lin g and as s e m b l y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
prelim inary technical data adf7020 r e v. pr h | pa g e 9 of 40 pin conf iguration and fu nction descriptions 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 adf7020 top view (not to scale) vcoin vreg1 vdd1 rfout rfgnd rfin rfinb r lna vdd4 rset vreg4 gnd4 mi x _ i mi x _ i mi x _ q mi x _ q filt_i filt_i gnd4 filt_q filt_q gnd4 test_a ce clkout data clk data i/o int/lock vdd2 vreg2 adcin gnd2 sclk sread sdata sle cv co gnd1 gnd vco gnd gnd vd d cp out vr eg3 v dd3 osc1 osc2 mux o ut 1 2 3 4 5 6 7 8 9 10 11 12 pin 1 indicator 01975-p r g-004 f i gure 4. pin config ur ation ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin no. mneonic function 1 vcoin the tuning voltage on this pin deter mines the output freq uency of the vo ltage control l ed osc i llator ( v co) . the higher the tuning voltage, th e higher the output freq uency . 2 vreg1 regulator voltage for pa block. a 100 nf capacitor sh ould be placed between thi s pin and ground for regulator stabili ty and noise rejection. 3 vdd1 voltage supply for pa block. dec o upling ca pacit o rs (x7r or tantalum) of 0.1 f and 0.01 f should be placed as clo s e as pos si ble to this pin. 4 rfout the modulated signal i s avai lab l e at this pin. output power levels are from ?20 dbm to + 13 dbm. the output should be impe d ance matched to the d e sired load usin g suitable compo n ents. see the transmi tter section. 5 rfgnd ground for output stage of tra n smitter. 6 rfin lna input for r e ceiver section. in put matching is req u ired between the antenna and the differe ntial lna input to ensure maximum powe r transfe r. see the lna/pa match i ng section. 7 rfinb complementary lna input. s ee the lna/pa ma t c hing section. 8 r ln a external bias resistor for lna. optimum resistor is 1.1 k? with 5% tolerance. 9 vdd4 voltage supply f o r lna/mixer block. t h is pin sh ould be decoupl e d to ground wi th a 0.01 f capacitor. 10 rset external resistor to set charge pump current and some internal bias cu rrents. use 3.6 k? with 5% tolerance. 11 vreg4 regulator voltage for lna/mixer bloc k. a 100 nf capacitor should be pl aced between this pi n and gnd for regulator stabili ty and noise rejection. 12 gnd4 ground for lna/mixer block. 13C18 mix/filt signal chain tes t pins. these pin s are high impe d an ce under normal conditio n s and should be l e ft unconnected. 19, 22 gnd4 ground for lna/mixer block. 20, 21, 23 filt/test_ a signal chain tes t pins. these pin s are high impe d an ce under normal conditio n s and should be l e ft unconnected. 24 ce chip enable. bri n ging ce low pu ts the adf7020 i n to comp lete power-down. register values are lost when ce is low, and the part must be reprogrammed onc e ce is brought high. 25 sle load enable, c m os input. when le goes high, the data stored in the shift registers is lo aded into one of the four latches. a latch is sele cted using the control bits. 26 sdata serial data inpu t. the serial data is loaded msb first with the two lsbs as the cont rol bits. this pi n is a high impedance cm os input. 27 sread serial data output. this pi n is used to feed readback data from the adf7020 to the microcontroller. the sclk input is used to clock e a ch read back bit (afc, adc readback) from the sread p i n. 28 sclk se ria l cl oc k in put. th is s e ria l c l oc k is used to clock in the seri al data to the registers. the data is latched into the 24-bit shift register on the clk rising edge. t h is pin i s a digital cmos input.
adf7020 preliminary technical data rev. prh | page 10 of 40 pin no. mnemonic function 29 gnd2 ground for digital section. 30 adcin analog-to-digital converter input. the internal 7-bit adc can be accessed through this pin. full scale is 0 to 1.9 v. readback is made using the sread pin. 31 vreg2 regulator voltage for digital block. a 100 nf capacitor should be placed between this pin and ground for regulator stability and noise rejection. 32 vdd2 voltage supply for digital block. a decoupling capacitor (x7r or tantalum) of 0.01 f should be placed as close as possible to this pin. 33 int/lock bidirectional pin. in output mode (int errupt mode), the adf7020 asserts the int/ lock pin when it has found a match for the preamble sequence. in input mode (lock mode), the micro controller can be used to lock th e demodulator threshold when a valid preamble has been detected. once the threshold is locked , nrz data can be reliably received. in this mode, a demod lock can be asserted with minimum delay. 34 data i/o transmit data input/re ceived data output. this is a digital pin and normal cmos levels apply. 35 data clk in receive mode, the pin outputs the synchronized data clock. the positive clock edge is matched to the center of the received data. in gfsk transmit mode, the pin outputs an accurate clock to latch the da ta from the microcontroller into the transmit section at the exact requir ed data rate. see the gaussian frequ ency shift keying (gfsk) section. 36 clkout a divided-down version of the crystal reference with output driver. the digital cl ock output can be used to drive several other cmos inputs such as a microcont roller clock. the output has a 50:50 mark-space ratio. 37 muxout this pin provides the lock_detect si gnal, which is used to determine if the pll is locked to the correct frequency. other signals include regulator_ready, which is an indicator of the status of the serial interface regulator. 38 osc2 the reference crystal should be connected between th is pin and osc1. a tcxo reference can be used by driving this pin with cmos levels an d disabling the crystal oscillator. 39 osc1 the reference crystal should be connected between this pin and osc2. 40 vdd3 voltage supply for the charge pump and pll dividers. this pin should be decoupled to ground with a 0.01 f capacitor. 41 vreg3 regulator voltage for charge pump and pll dividers. a 100 nf capacitor sh ould be placed between this pin and ground for regulator stab ility and noise rejection. 42 cpout charge pump output. this output ge nerates current pulses that are in tegrated in the loop filter. the integrated current changes the control voltage on the input to the vco. 43 vdd voltage supply for vco tank circuit. this pin sh ould be decoupled to ground with a 0.01 f capacitor. 44C47 gnd grounds for vco block. 48 cvco a 22 nf capacitor should be placed be tween this pin and vreg1 to reduce vco noise.
prelim inary technical data adf7020 r e v. pr h | pa g e 11 o f 40 frequency synthesizer reference input section the o n -bo a rd cr ys tal os cil l a t o r cir c ui tr y (f igur e 5) ca n us e an in exp e n s i v e quar tz cr ys t a l as t h e p ll r e fer e n c e . the os ci l l a t o r cir c ui t is ena b le d b y s e t t in g r1_ d b12 hig h . i t is ena b le d b y defa u l t on p o w e r - u p an d is dis a b l e d b y b r in g i ng ce lo w . er r o rs in t h e cr ys tal can b e co r r ec t e d usin g th e a u t o ma tic f r eq uen c y co n t r o l (s e e t h e afc s e c t ion) fe a t ur e o r b y ad j u s t in g t h e f r ac t i o n a l -n va lue (s e e t h e n c o un ter s e c t ion). a sin g le-e nde d re f e re nc e ( t c x o , c x o ) c a n a l s o b e u s e d . t h e c m o s l e vel s s h o u ld b e a p p l ie d t o osc2 wi t h r1_d b12 s e t lo w . os c 1 cp1 cp2 os c 2 01975-p r g-005 f i g u re 5. o s c i l l at or circuit on t h e a d f7 02 0 t w o p a ralle l r e s o n a n t ca p a ci t o rs a r e r e q u ir ed f o r oscilla t io n a t t h e co r r e c t f r e q uen c y ; t h eir val u es a r e dep e n d e n t o n t h e cr ys t a l s p e c if ic a t ion. the y s h o u l d b e ch os en s o t h a t t h e s e r i es val u e o f ca p a c i t a n c e add e d t o t h e pcb t r ack c a p a ci t a n c e adds u p t o t h e loa d ca pa ci ta n c e o f th e cr ys tal , us uall y 20 pf . t r a c k ca pa ci ta n c e val u es va r y f r o m 2 pf t o 5 pf , dep e n d in g on b o a r d la yo u t . w h er e p o s s ib le , ch o o s e ca p a c i to rs t h a t ha ve a ver y l o w t e m p era t ur e co ef f i cien t t o en s u r e s t a b le f r e q ue n c y o p era t i o n ove r a l l c o nd i t i o ns . clk o ut divider a n d buff er the cl k o u t c i r c ui t t a k e s t h e r e fer e n c e clo c k sig n al f r o m t h e o s ci l l a t o r s e c t ion, sh own in f i g u r e 5, a n d su p p l i es a divid e d - do wn 50:50 mark-s p a ce sig n al t o th e cl k o u t p i n . an ev en divide f r o m 2 t o 30 is a v a i la b l e . this d i vi de n u m b er is s e t in r1_d b(8:11). on p o w e r - u p , t h e clk o ut defa u l ts t o divide -b y - 8. dv dd clk out enable bit clk out osc1 divider 1 to 15 01975-p r g-006 2 fi g u r e 6 . c l k ou t stage t o dis a b l e cl k o u t , s e t t h e divide n u m b er t o 0. th e o u t p u t b u f f er ca n dr i v e u p t o a 20 pf load wi t h a 10 % r i s e t i m e a t 4 . 8 m h z. f a s t e r e d ge s c a n re su lt in s o me sp u r iou s fe e d t h rou g h t o th e o u t p u t . a smal l s e r i es r e si s t o r (50 ?) ca n be us e d t o s l o w t h e clo c k e d g e s t o r e d u ce t h es e s p urs a t f clk . r c o unter the 3- b i t r co u n t e r di vi des t h e r e fer e n c e i n p u t f r e q uen c y b y a n in teg e r f r o m 1 to 7. th e divide d-do w n sig n al is p r es en t e d as t h e r e fer e n c e clo c k t o t h e phas e f r e q uen c y dete c t o r (p fd). th e divide r a t i o is s e t in reg i ster 1. m a x i mi zi n g t h e pf d f r e q uen c y r e d u ces t h e n v a l u e . this r e d u c e s t h e n o is e m u l t i p lie d a t a ra te of 2 0 l o g ( n ) to t h e output , a s w e l l a s re d u c i ng o c c u r r e n c e s of sp ur io us co m p on e n ts. th e r r e g i st er defa u l ts to r = 1 o n po w e r - u p : pf d [h z ] = xt a l / r mux o ut a n d l o ck d e t e c t the mu x o ut p i n al lo ws t h e us er t o acces s va r i o u s dig i t a l p o in ts in t h e ad f7020. th e st a t e o f mux o ut is co n t r o l l ed b y b i ts r0_d b(29: 31). re g u l a t o r re a d y regu l a t o r read y is t h e defa u l t s e t t in g o n mux o u t a f t e r t h e t r a n s c ei v e r has b e en p o w e r e d u p . the p o w e r - u p t i m e o f t h e r e gu la t o r is typ i cal l y 50 s. b e ca us e t h e s e r i al i n t e r f ace is p o we re d f r om t h e re g u l a tor , t h e re g u l a tor m u st b e a t it s nom i n a l v o l t a g e bef o r e th e ad f7020 can b e p r og ra mmed . th e s t a t us of t h e r e gu l a to r c a n b e m o ni to r e d a t mu x o u t . w h en t h e regu l a t o r read y sig n al o n mu x o ut is hig h , p r og ra mmin g of th e ad f7020 ca n b e g i n. regulator ready digital lock detect a nalog lock detec t r counter output n counter output pll test modes - ? test modes mux control dgnd dv dd muxout 01975-p r g-007 f i gure 7. mu x o u t circuit digital l o ck d e t e c t dig i tal lo ck dete c t is ac ti v e hig h . th e lo c k det e c t cir c ui t is lo ca te d a t t h e pfd . w h en t h e phas e er r o r o n f i v e co n s e c u t i v e c y cl es is l e ss t h a n 1 5 ns , l o ck de te c t is s e t hig h . l o ck dete c t r e ma in s hig h u n t i l 25 n s phas e er r o r is det e c t e d a t t h e p f d . b e ca us e n o ext e r n al co m p on e n t s a r e n e e d e d fo r dig i t a l lo ck dete c t , i t is m o r e wi dely us e d t h a n a n a l o g lo ck dete c t .
adf7020 prelim inary technical data r e v. pr h | pa g e 12 o f 40 an a l og l o c k d e t e c t t h i s n - ch an n e l op e n - d r a i n l o c k d e te c t s h ou l d b e op e r a t e d w i t h a n ext e r n al p u l l - u p r e sis t o r o f 10 k? n o minal . w h en a lo c k has been det e c t e d , this o u t p u t is hig h wi th na r r o w l o w-g o in g p u ls es . v o ltage r e g u l a t o rs the ad f7020 c o n t a i n s f o ur r e gu la t o rs t o s u p p ly s t a b le v o l t a g es t o t h e p a r t . th e n o minal r e gu l a to r v o l t a g e is 2.3 v . e a ch r e gu la t o r sh o u l d ha ve a 100 nf ca p a c i t o r co nn e c t e d betw een vreg an d gnd . w h en ce is hig h , t h e r e gu l a to rs a n d o t h e r a s s o c i ate d c i rc u i t r y are p o we re d on , d r aw i n g a tot a l supp ly c u r r en t o f 2 ma. br in g i n g t h e chi p -enab l e p i n l o w dis a b l es t h e re g u l a tors , re d u c e s t h e su p p ly c u r r e n t to l e ss t h an 1 a , and eras es al l val u es h e l d in t h e r e g i s t ers. th e s e r i al in t e r f ace o p era t es o f f a r e gu la t o r s u p p l y ; t h er efo r e , t o wr i t e t o t h e p a r t , t h e us er m u st ha v e ce hig h and t h e r e gu l a t o r v o l t a g e m u s t b e st a b i l i z e d . regu la to r st a t us (vr e g4) ca n b e m o ni to r e d usin g t h e re g u l a tor re a d y s i g n a l f r om m u x o u t . l o op f ilt er the lo o p f i l t er i n t e g r a t es t h e c u r r en t p u ls es f r o m t h e cha r g e p u m p t o f o rm a v o l t a g e tha t t u n e s th e o u t p u t o f th e v c o t o th e desir e d f r e q uenc y . i t a l s o a t ten u a t es sp ur io us le vels gen e r a te d b y th e pll. a typ i c a l lo o p f i l t er desig n is sh o w n in f i gur e 8. 01975-p r g-008 charge pump out vco f i g u re 8. t y pic a l l o op f ilt er conf ig u r a t ion i n fs k, t h e lo o p s h o u ld be desig n e d s o tha t the lo o p ban d wid t h (lb w ) is a p p r o x ima t e l y f i v e tim e s t h e da ta r a te . w i denin g t h e lb w exces s i v e l y r e d u ces th e t i m e s p en t j u m p in g betw e e n f r e q uen c ies, b u t ca n ca us e in suf f icien t sp ur io us a t t e n u a t io n. f o r a s k syst ems, a wider lb w is r e co mme n d e d . th e s u dden la rge t r a n si t i on b e tw e e n tw o p o w e r le v e l s mig h t r e su l t in v c o p u l l in g an d ca n ca us e a wider ou t p ut sp e c t r um t h a n is desir e d . b y w i d e ni n g t h e l b w t o m o r e th a n 10 tim e s t h e da ta ra t e , t h e amou n t of v c o pu l l i n g i s re d u c e d, b e c a u s e t h e l o op s e tt l e s q u ic kl y back t o th e co r r ec t f r eq uen c y . th e wider lb w mig h t r e st r i c t t h e o u t p u t p o w e r a nd da t a r a te o f as k- b a s e d sy stem s co m p a r ed wi th fs k - b a se d s y s t em s . n a r r ow - l o o p b a nd w i d t hs c a n re su lt i n t h e l o op t a k i ng l o ng p e r i o d s o f time t o a t ta in lo c k . c a r e f u l desig n o f th e lo o p f i l t er is cr i t ica l t o ob t a i n in g acc u ra t e f s k/gf s k m o d u la t i on. f o r gfs k , i t is r e co mm en de d t h a t an lb w o f 2.0 t o 2.5 tim e s t h e da t a r a t e b e us e d t o en s u r e t h a t s u f f i cien t s a m p les a r e t a k e n o f t h e in p u t da t a w h i l e f i l t er in g sys t em n o is e . th e f r e e desig n to ol a d i s i m pl l c a n b e u s e d to de s i g n l o op f i lt e r s for t h e ad f7020. n counter the f e e d bac k divider in t h e ad f7020 p ll co n s is ts o f a n 8-b i t in teger co un ter a nd a 14 -b i t - ? f r ac t i o n a l -n divider . t h e in teger co un ter is t h e st anda r d p u ls e-swa l lo w t y p e co m m on in plls. this s e ts t h e m i ni m u m in teger divi de va lue to 31. th e f r ac tio n al di vide val u e g i v e s v e r y f i n e r e s o l u tion a t t h e o u t p u t , w h er e t h e o u t p u t f r e q uen c y o f t h e pll is calc u l a t e d as f ou t = r xtal ( in t e g e r - n + 14 2 -n fractional ) 01975-p r g-009 vco 4n third-order 6 - ' modulator pfd/ charge pump 4r integer-n fractional-n reference in f i g u re 9. f r ac t i on a l -n pll the com b ina t ion o f th e in teg e r - n (m axim u m = 255) a n d t h e f r ac tio n al-n (maxim um = 1638 3/16384) g i v e a m a xim u m n divider o f 255 + 1. th er efo r e , the m i nim u m us a b le p f d is pdf min [h z ] = ma x i m u m r e q u i r e d o u t p u t fr e q u e n c y /(255 + 1) f o r exa m p l e , wh en o p era t in g in the e u r o p e a n 868 mh z t o 870 mh z b a n d , pf d min eq uals 3.4 mh z. v o ltage controlled oscillator ( v c o ) t o mi nimize spur io us emissio n s, t h e o n -chi p v c o o p er a t es f r o m 1732 mh z t o 1856 mh z. the v c o sig n al is th en divided b y 2 t o gi v e th e r e q u i r ed f r eq u e n c y f o r th e tra n s m i t t e r a n d t h e r e q u ir e d l o f r e q uen c y fo r t h e re cei v er . the v c o sh o u l d b e r e cen t er e d , dep e n d in g on t h e r e q u ir e d f r eq uen c y o f o p era t io n , b y p r ogra m m i n g t h e v c o ad j u st b i ts r1_d b(20:21). the v c o is enab le d as p a r t o f t h e pll b y t h e pll - enab le b i t, r0_d b28. a f u r t h e r f r e q uen c y divide-b y- 2 is in cl ude d t o a l lo w o p era t io n in t h e lo w e r 433 mh z and 460 mh z b a n d s. t o ena b le o p er a t ion in t h e t h es e b a nds, r1_d b13 sho u ld b e s e t t o 1. the v c o n e e d s a n ext e r n al 22 nf b e twe e n t h e v c o an d t h e regu la t o r t o r e d u ce in t e r n a l n o is e .
prelim inary technical data adf7020 r e v. pr h | pa g e 13 o f 40 vc o b i a s c u r r e n t v c o b i a s cu rr e n t ca n be ad j u s t ed u s i n g b i ts r 1 _ d b 1 9 t o r1 _db1 6 . t o e n sur e v c o o s c i l l a t ion, t h e min i m u m bias c u r r en t s e t t in g un der typ i cal co n d i t io ns is 2.5 m a . vco loop filter mux vco select bit to pa and n divider vco bias r1_db (16:19) 220 f 01975-p r g-010 cvco pin 2 2 f i gure 10. v o ltage contro l l ed o s ci ll ator ( v c o ) choos ing channels for best s y stem performa nce t h e f r ac tio n al-n p ll al lo ws the s e lec t io n o f a n y c h a nne l wi thin 868 mh z t o 928 mh z (and 433 mh z usin g divide-b y-2) t o a re s o lut i on of < 1 0 0 hz . t h i s a l s o f a c i l i t a te s f r e q u e nc y ho ppi n g sys t em s. c a r e f u l s e lec t io n o f th e rf transm i t c h anne ls m u s t be m a de to achie v e b e st sp u r iou s p e r f o r ma nc e. t h e archite c t u re of f r a c ti o n al- n r e s u l t s i n so m e lev e l o f th e n e a r e s t i n t e g e r c h a n n e l m o vi n g t h r o ug h t h e lo o p t o t h e rf o u t p u t . thes e b e a t- n o t e sp urs a r e n o t a t ten u a t e d b y t h e lo o p , if t h e desire d rf cha n ne l an d t h e ne are s t i n t e ge r ch an n e l are s e p a r a te d b y a f r e q u e nc y of les s tha n t h e lb w . the o c c u r r en ce o f b e a t - n o t e spurs is ra r e , b e ca us e t h e i n teg e r f r e q uen c ies a r e a t m u l t i p les o f t h e r e fer e nce , w h ich is ty p i ca l l y >10 mh z. b e a t -n ot e sp urs ca n be sig n if ican t l y r e d u ced in a m p l i t ude b y a v o i din g v e r y sm al l o r v e r y la r g e val u es in t h e f r ac tio n al re g i ste r , u s i n g t h e f r e q u e nc y d o ubl e r . by h a v i ng a ch an ne l 1 mh z a w a y f r o m a n in t e g e r f r eq uen c y , a 100 kh z lo o p f i l t er ca n r e d u ce t h e l e v e l t o adf7020 prelim inary technical data r e v. pr h | pa g e 14 o f 40 transmitter rf output st a g e the p a o f th e ad f7020 is bas e d o n a sin g le-ended , con t r o l l ed c u r r en t, o p en- d ra in am plif ier t h a t has b e en de sig n e d t o de l i v e r u p t o 13 db m in t o a 50 ? lo ad a t a m a xim u m f r eq uen c y o f 928 mh z. the p a o u t p u t c u r r en t a n d , co n s e q ue n t ly , t h e o u t p u t p o w e r a r e p r og ra mma b l e o v er a wide rang e . the p a co nf igura t io n s i n f s k/gf sk and a s k/o o k m o d u la t i on m o des ar e sh o w n i n f i gur e 11 a n d f i gur e 12, r e s p ec ti v e l y . i n fs k/gfs k m o d u la t i on m o de , t h e o u t p u t p o w e r is inde p e nden t o f t h e st a t e o f t h e d a t a _io p i n. i n a s k / o o k mo d u l a t i on m o de, i t is dep e nden t o n t h e st a t e o f t h e d a t a _io p i n an d bi t r2_db29, which s e lec t s t h e p o la r i ty o f t h e txd a t a in p u t. f o r eac h t r a n smis sion m o d e , t h e o u tpu t p o w e r ca n b e ad j u ste d as fol l o w s: ? fs k/gfsk: th e o u t p u t p o w e r is s e t usin g b i ts r2_d b(9:14). ? a s k: th e o u t p u t p o w e r fo r t h e i n ac t i v e st a t e o f t h e txda t a in p u t is s e t b y bi ts r2_d b(15:2 0 ). th e o u t p u t p o w e r fo r t h e a c ti v e s t a t e o f th e t x da ta in p u t i s se t b y b i t s r2_ d b ( 9:14). ? o o k : th e o u t p u t po w e r f o r th e a c ti v e s t a t e o f th e t x da ta in p u t is s e t b y bi ts r2_d b(9:14) . th e p a is m u te d w h e n t h e txd a t a i n p u t is inac t i v e . idac 2 6 r2_db(9:14) r2_db4 r2_db5 digital lock detect r2_db(30:31) + rfgnd rfout from vco 01975-p r g-011 f i gur e 1 1 . p a c o nf igur a t io n i n fsk/ gfsk m o de idac r2_db(9:14) r2_db(15:23) r2_db4 r2_db5 digital lock detect r2_db(30:31) r2_db29 + rfgnd rfout from vco 01975-p r g-012 6 6 6 0 ask/ook mode data i/ o f i gur e 1 2 . p a c o nf igur a t io n i n ask / o o k m o de the p a is e q u i pp e d wi t h o v er v o l t a g e p r o t e c t i on, which ma k e s i t ro bu st i n s e ve re mi s m a t c h c o nd it i o ns . d e p e nd i n g on t h e ap p l i c at i o n , o n e c a n d e s i g n a m a t c h i n g n e t w o r k f o r t h e p a t o exhi b i t o p t i m u m ef f i cien c y a t t h e desir e d radi a t e d o u t p u t p o wer le v e l fo r a wide ra n g e o f dif f er en t an ten n as, such as lo o p o r m o n o p o le an te nnas. s e e t h e l n a / p a m a tch i n g s e c t ion fo r det a i l s. p a bias c u rren ts a n d mute p a until l o ck bi t c o n t r o l b i ts r2 _d b(30:31) facili ta t e an ad j u s t m e n t o f the p a b i as c u r r en t t o f u r t h e r ext e nd t h e o u t p u t p o w e r co n t r o l ra n g e , if n e ce ss a r y . i f t h is fe a t ur e is n o t re q u ir e d , t h e def a u l t va l u e o f 7 a is r e co mmen de d . the o u t p u t st a g e is p o wer e d do wn b y re s e tt i n g b i t r 2 _ d b 4 . t o re d u c e t h e l e vel of u n d e s i re d spu r i o u s emissio n s, t h e p a can b e m u t e d d u r i n g t h e p l l lo ck phas e b y s e t t in g b i t r2_d b5 (m u t e p a un til lo c k b i t). modulation scheme s f r equ e nc y shif t k e ying (fsk ) f r e q uen c y shif t k e ying is im ple m e n t e d b y s e t t i n g t h e n va l u e fo r t h e cen t er f r e q uen c y and t h en t o g g l in g t h is wi t h t h e txda t a lin e . th e de vi a t i o n f r o m t h e cen t er f r e q uen c y is s e t usin g b i ts r2_d b(15:23). the devia t ion f r o m the cen t er f r eq uen c y in h z is 14 2 hz] [ number m odulation pfd fsk deviation = wher e mo d u l a t i o n n u mb e r is a n u m b er f r o m 1 t o 511 (r2_d b (15:23)) . s e lec t fs k using b i ts r2_d b(6: 8). 01975-p r g-013 vco n third-order - ? modulator pfd/ charge pump 4r integer-n fractional-n pa stage ?f dev +f dev txdata fsk deviation frequency f i gure 13. fsk imp l em entati on
prelim inary technical data adf7020 r e v. pr h | pa g e 15 o f 40 g aus s i an fre q uen c y s h ift ke ying ( g fsk) g a u s s i an f r e q u e nc y sh i f t ke y i ng re d u c e s t h e b a nd w i d t h occu p i e d b y th e tra n s m i t t e d s p e c tr u m b y d i gi tal l y p r e f il t e ri n g t h e t x d a t a . a t x c l k output l i ne i s prov i d e d f r om t h e ad f7020 fo r syn c hr o n iza t ion of txda t a f r o m th e micr o - co n t r o l l er . t h e t x clk l i n e can be co nnec t e d to th e c l o c k in p u t o f a s h i f t r e gi s t er th a t c l oc k s da t a t o th e tra n s m i t t e r a t t h e e x a c t da ta r a t e . setting up the adf7020 for gfsk t o s e t u p t h e f r e q uen c y de v i a t ion, s e t t h e p f d and t h e m o d co n t r o l b i ts: 12 2 2 ] hz [ m deviation pfd gfsk = wher e m is gfsk_m o d _c ontr o l s e t using r2_d b(24:26). t o s e t u p th e g f s k d a ta r a t e : counter index factor divider pfd dr _ _ ] bps [ = f o r f u r t h e r info r m a t io n, s e e t h e a p plic a t ion n o te , us i n g g f s k on t h e a d f 7 0 1 0 , in t h e e v al -ad f 7010eb1 t e chnical n o te . amplitud e shift keying (ask) am pli t ude shif t k e yin g is im ple m e n t e d b y s w i t chin g t h e o u t p u t s t a g e betw een tw o dis c r e t e p o wer lev e ls. t h is is acco m p lish e d b y t o g g l in g th e d a c, which co n t r o ls th e o u t p u t lev e l betw een tw o 6- b i t v a l u es s e t u p in r e g i s t er 2. a zer o tx da t a b i t s e nds b i ts r2_d b(15: 20) t o th e d a c. a hig h txd a t a b i t s e n d s b i ts r2_d b(9:14) t o th e d a c. a m a xim u m m o d u l a tio n dep t h o f 30 db is p o ssib le . on-off k e ying (ook ) on -o f f k e yin g is im p l em en t e d b y swi t c h in g the o u t p u t s t a g e to a cer t a i n p o w e r le v e l f o r a hig h txda ta b i t and s w i t c h in g t h e o u t p u t s t a g e o f f f o r a zer o . f o r o o k , th e tran sm i t t e d po w e r f o r a hig h in p u t is p r og ra m m ed usin g b i ts r2 _d b(9:14). g aus s i an on - o ff ke ying ( g - o o k ) ga us sia n o n -o f f k e yin g r e p r esen ts a p r ef il t e r e d f o r m o f o o k m o d u la ti o n . th e u s u a ll y s h a r p s y m b o l tra n s i tio n s a r e r e p l a c e d wi t h s m o o t h ga us sia n f i l t er ed t r a n si t i o n s, t h e res u l t b e in g a r e d u cti o n in f r eq u e n c y p u ll i n g o f th e v c o . f r eq u e n c y p u ll i n g o f t h e v c o i n o o k m o de can le ad to a wider t h a n desir e d b w , es p e c i al l y if i t is n o t p o s s i b le t o in cr ease t h e lo o p f i l t er b w > 300 kh z. th e g-o o k s a m p ling c l o c k s a m p les da ta a t t h e da t a ra t e . (s ee t h e s e t t in g u p t h e adf7020 fo r gfs k s e c t io n.)
adf7020 prelim inary technical data r e v. pr h | pa g e 16 o f 40 receiver section rf front end the ad f7020 is bas e d o n a f u l l y in t e g r a t e d , lo w if r e cei v er a r c h i t ec t u r e . the lo w if a r c h i t e c t u r e facili ta t e s a v e r y lo w ext e r n al co m p on e n t co u n t and do es n o t s u f f er f r o m p o w e r - li n e - ind u ce d in t e r f er en c e p r ob lem s . f i gur e 14 sh o w s t h e st r u c t ur e o f t h e r e ceiv er f r o n t e n d . th e ma n y p r og ra mmin g o p t i on s al lo w us ers t o t r a d e o f f s e n s i t ivi t y , l i ne ar it y , a n d c u r r e n t c o nsu m pt i o n ag ai nst e a ch ot he r i n t h e wa y b e st su i t abl e for t h eir a p pl i c a t ions . t o ac hi e v e a hig h l e vel o f r e silien ce a g ain s t sp ur io us r e cep t io n, t h e ln a f e a t ur es a dif f er en t i al in pu t. s w i t ch s w 2 sh o r ts t h e l n a i n p u t w h en tra n sm i t m o de is s e lec t e d (r0_ d b 27 = 0). this fea t ur e facili t a t e s t h e desig n o f a co m b in e d ln a/p a ma t c hin g n e tw o r k, a v o i din g t h e n e e d fo r a n ext e r n al rx/tx s w i t ch. s e e t h e l n a/p a m a t c h i n g secti o n f o r d e ta ils o n th e d e s i g n o f th e m a t c h i n g ne t w or k . 01975-p r g-014 sw2 lna rfin rfinb tx/rx select [r0_db27] lna mode [r6_db15] lna current [r6_db(16:17)] mixer linearity [r6_db18] lo i (to filter) q (to filter) lna gain [r9_db(20:21)] lna/mixer enable [r8_db6] f i g u re 14. a d f7 02 0 r f f r ont e n d t h e ln a is f o l l o w ed b y a q u adra t u r e d o wn co n v er sio n m i x e r , whic h con v er ts th e rf sig n al t o th e if f r eq uen c y o f 200 kh z. i t is im p o r t an t t o co n s ider t h a t t h e o u t p ut f r e q uen c y o f t h e syn t h e sizer m u st be p r og ra m m e d t o a val u e 200 kh z be lo w the cen t er f r e q ue n c y o f t h e r e cei v e d cha n ne l. the l n a has t w o b a sic o p era t in g m o des: hig h ga in/lo w n o is e m o de and lo w ga in/lo w p o w e r m o de . t o s w i t ch b e tw e e n t h es e tw o m o des, us e t h e l n a_ m o de b i t, r6_d b15. th e mixer is als o co nf igura b le betw een a lo w c u r r en t an d a n enha n c ed lin e a r i t y m o de usin g t h e m i xer_lin e a r i t y b i t, r6_d b18. b a s e d o n t h e sp e c if ic s e n s i t iv i t y a n d li n e a r i t y r e q u ir em e n ts o f t h e a p plic a t ion, i t is r e co mm e n de d t o a d j u st con t r o l b i ts ln a_ m o de (r6 _ d b 15) a n d m i xer_lin e a r i t y (r6_d b 18) as out l i n e d i n t a bl e 5 . the ga i n o f t h e ln a is conf igur e d b y t h e ln a_ ga in f i e l d , r9_d b(20:21), a n d can b e s e t b y ei t h er t h e us er o r t h e a g c log i c. if filter s e ttings/calibratio n o u t-o f -b and i n ter f er en ce is r e j e c t e d b y m e a n s of a fo ur t h -o r d er b u t t er w o r t h p o lyphas e if f i l t er cen t er e d a r o u nd a f r e q ue n c y o f 200 kh z. th e b a ndwid t h o f the if f i l t er ca n be p r og ra m m e d betw een 100 kh z and 200 kh z b y m e an s o f c o n t r o l b i ts r1_d b(22:23), a n d sh o u ld be ch os en as a com p r o m i s e b e tween in t e r f er en c e r e j e c t io n, a t t e n u a t i o n o f t h e desir e d sig n al, an d t h e af c p u l l -i n r a nge. t o co m p en s a te fo r ma n u fac t ur i n g t o lera n c e s , t h e if f i l t er s h o u ld b e cal i b r a t e d o n ce a f t e r p o w e r - u p . th e i f f i l t er calib r a t io n log i c r e q u ir es tha t t h e if f i l t er divider in b i ts r6_d b(20:28) be s e t dep e n d en t o n t h e cr ys tal f r eq uen c y . on c e ini t i a t e d b y s e t t i n g b i t r6_d b1 9, t h e ca l i b r a t ion is p e r f o r m e d a u t o ma ticall y wi th o u t a n y u s e r i n t e r v e n ti o n . th e cali b r a t i o n tim e is 200 s, d u r i n g whic h t h e ad f7020 s h o u l d n o t be acces s e d . i t is im p o r t a n t n o t t o ini t ia t e t h e calib r a t io n c y c l e bef o r e the cr ys tal os cil l a t o r has f u l l y s e t t led . i f th e a g c lo o p is dis a b l e d , t h e gai n o f if f i l t er ca n b e se t t o th r ee lev e ls u s i n g th e f i l t er_ga i n f i e l d , r9_d b(20:21). the f i l t er ga in is ad j u s t e d a u t o ma tical l y , if th e a g c lo o p is ena b led. the sig n al i n t h e ima g e cha n ne l o f t h e lo w if mixer , lo ca t e d a t a f r eq uen c y o f 400 kh z b e lo w the desir e d c h anne l , is r e jec t e d d u e t o t h e i m a g e r e j e c t io n o f t h e p o lyphas e f i l t er . th e i m a g e r e j e c t io n p e r f o r ma nce o f t h e if f i l t er is su b j e c t t o ma n u fac t ur - i n g tol e r a nc e s , and, to s o me e x te n t , te m p e r a t u r e dr i f t . t o im p r o v e t h e ima g e r e j e c t ion, a ca lib r a t ion p r o c e d ur e can b e p e r f o r m e d as ou t l in e d i n t h e i m a g e rej e c t io n c a li b r a t io n secti o n . table 5. lna/ mixer mod e s receiver mode lna m o d e (r6_d b 1 5 ) lna gain v a lue r9_db ( 2 1 :2 0) mixer lin earity (r6_d b 1 8 ) sensit ivity (dr = 9.6 kbp s , f de v = 10 kh z) rx curr ent consumpt ion (ma) input ip 3 (d bm) high sensitivity mode (defaul t ) 0 3 0 0 ? 1 1 0 . 5 2 2 ? 3 5 r x m o d e 2 1 1 0 0 ? 1 0 4 2 0 ? 1 5 . 9 l o w c u r r e n t mo d e 1 3 0 ? 9 1 1 9 ? 3 . 2 enhan c e d l i n e a r i t y m o d e 1 3 1 ? 1 0 1 1 9 6 . 8 r x m o d e 5 1 1 0 1 t b d t b d ? 8 . 2 5 r x m o d e 6 0 3 0 1 t b d t b d ? 2 8 . 8
prelim inary technical data adf7020 r e v. pr h | pa g e 17 o f 40 rssi/agc section t h e rss i is im plem en t e d as a succes s i v e co m p r e s s io n log a m p fol l o w in g t h e b a s e -b and cha n nel f i l t er in g. th e l o g a m p achi e v e s 3 db log lin e a r i t y . i t als o do u b l e s as a limi t e r t o co n v er t t h e s i gn al - t o - d i gi tal l e v e l s f o r th e fs k d e m o d u la t o r . t h e r s s i i t se lf is us e d fo r a m p l i t ude s h if t k e y i ng (a s k ) de m o d u la t i on. i n as k m o de , ext r a dig i t a l f i l t er in g is p e r f o r m e d on t h e rss i val u e . of fs et co r r ec tio n is ac hiev e d usin g a s w i t ch e d c a p a ci t o r in teg r a - t o r in fe e d b a ck a r o u n d t h e log a m p . this us es t h e b b o f fs et clo c k divide . the rss i le ve l is c o n v er t e d fo r us er r e ad b a ck an d dig i t a l l y co n t r o l l ed a g c b y an 80-lev e l (7-b i t ) f l as h ad c. t h is lev e l c a n be co n v er t e d t o in p u t p o w e r in dbm . 1 ifwr ifwr ifwr ifwr latch aaa r clk adc offset correction rssi ask demod fsk demod 01975-p r g-015 f i g u re 15. r ssi b l o c k d i ag r a m rssi thresholds w h en t h e r s s i is a b o v e a g c_ hi gh_ t hre s h o ld , t h e gain is r e d u ce d . w h e n t h e rs s i is b e lo w a g c_ l o w_ thre s h o l d , t h e ga i n is i n cr e a s e d . a del a y (a gc_d el a y ) is p r og ra mm e d t o al lo w fo r s e t t lin g o f t h e lo o p . th e us er p r og ra m s t h e tw o t h r e sh old va l u es ( r e c o m m e nde d def a u l ts, 27 and 76) a n d t h e de l a y (defa u lt, 10). th e de fa u l t a g c s e t u p val u es sh o u ld b e a d e q u a t e f o r m o s t ap p l i c at i o n s . t h e t h r e s h o l d v a l u e s mu s t b e ch os en t o b e mo r e t h a n 30 a p ar t fo r t h e a g c to o p era t e co r r ec tl y . offset correction clock i n reg i st er 3, t h e us er sh o u ld s e t t h e b b o f fs et clo c k divide b i ts r3_d b(4:5) t o g i v e a n o f fs et c l o c k between 1 mh z and 2 mh z, wher e: bb os _ c lk [h z ] = x t al/ ( bb os_cl k _d ivi d e ) bb os_clk_d i v id e can be s e t t o 4, 8, o r 16. agc informat ion i n reg i st er 9, the us er s h o u ld s e lec t a u t o ma tic g a in co n t r o l b y s e lec t in g a u t o in r9_d b18 and a u t o in r9_d b 19. th e us er s h o u ld t h en p r og ra m a g c lo w thr e sh old r9_db(4:10) a n d a g c hig h t h r e sh old r9_d b(11 :17). th e r e comm en ded/def a u l t val u es fo r t h e lo w an d hig h t h r e sh olds a r e 30 and 70, r e sp e c - t i v e ly. i n t h e a g c2 r e g i st er t h e us er sh o u l d p r og ra m t h e a g c de l a y t o b e lo n g en o u g h t o al lo w the lo o p t o s e t t le . th e r e c o mme nde d va l u e is 1 0 . r ssi f o rm ul a ( c on v e r t ing t o dbm) in p u t p o w e r [db m ] = ?110 db m + ( re a d ba c k _cod e + ga i n _ m o d e_ co rr e c t i o n ) 0.5 wher e: re a d ba c k _cod e is gi v e n b y b i ts r v 7 t o r v 1 in t h e r e ad back re g i ste r ( s e e r e a d b a c k f o r m a t s e c t i o n ) . ga i n _ m o d e_ co rr e c t i o n is g i v e n b y t h e val u es i n t a b l e 6. ln a gain and f i l t er ga in (l g2 /lg1, fg2/fg1) a r e a l s o ob t a i n e d f r om t h e re a d b a ck re g i ste r . table 6. gain mode correction table ln a gain (lg2, lg1) f i l t e r ga i n (fg2, fg 1) gain mode cor r ection h (10) h (10) 0 m (01 ) h (10) 11 m (01 ) m (01 ) 19 + 11 = 30 m (01 ) l (00) 19 + 19 + 11 = 49 l (00) l (00) 19 + 19 + 19 + 11 = 68 a n a d d i t i on a l f a c t or shou l d b e i n t r o d u c e d to a c c o u n t f o r l o ss e s i n t h e f r on t - e n d ma tch i ng ne t w or k / a n te n n a. fsk demodulators on the adf7020 the two fsk dem o dul a tors on the adf7020 are ? fsk correlator/d e m o d u lator ? line ar demo dul a tor select these us ing the dem o d s e lect bits, r4 _db(4:5). fsk c o rrelator/dem o dulat o r the q u adra t u r e o u t p u t s o f t h e i f f i l t er a r e f i rst limi te d and t h e n f e d to a p a i r of d i g i t a l f r e q u e nc y c o r r el a t or s t h at p e r f or m b a n d - p a ss f i l t er in g o f t h e b i na r y fs k f r e q uen c ies a t (if + f de v ) a n d (if ? f de v ). da t a is r e co v e r e d b y co m p a r in g the o u t p u t leve ls f r om e a c h of t h e t w o c o r r el ator s . t h e p e r f or m a nc e of t h i s f r e q u e n c y d i s c r i m i n a t o r ap p r ox i m at e s t h at o f a m a t c h e d f i l t e r det e c t o r , which is kn o w n t o p r o v ide op t i m u m det e c t io n in t h e p r es en c e o f a w gn. post demod filter data s y nchronize r if ? f dev if + f dev i if q limiters 0 db(4:13) db(8:15) db(14) rx data rx clk slicer frequency correlator 01975-p r g-016 f i gure 16. fsk co rrel a to r/ d e m o dul a tor b l ock d i agr a m
adf7020 prelim inary technical data r e v. pr h | pa g e 18 o f 40 pos tdemo dul ator filte r a s e co n d -o r d er , dig i tal lo w-p a ss f i l t er r e m o v e s exces s n o is e f r om t h e d e m o d u l a te d bit s t re a m at t h e output of t h e dis c r i min a to r . t h e b a n d wi d t h of t h is p o stde m o d u l a to r f i l t er is p r og ra mma b l e a n d m u st b e o p t i mi ze d fo r t h e u s er s da t a ra te . i f t h e b a ndwi d t h i s s e t t o o na r r o w , p e r f o r ma n c e is deg r ade d d u e to i n te rs y m b o l i n te r f e r e n c e ( i s i ) . i f t h e b a ndwi d t h i s s e t to o wide , excess n o i s e deg r ades t h e r e cei v er s p e r f o r ma nce . t y p i cal l y , th e 3 d b ban d wid t h o f this f i l t er is set a t a p p r o x ima t e l y 0.75 tim e s t h e us er s da ta r a t e , usin g b i ts r4_d b(6:15). bit slicer t h e re c e ive d d a t a i s re c o ve re d by t h re sho l d d e t e c t i n g t h e output o f t h e p o stde mo d u l a t o r lo w-p a ss f i l t er . i n t h e c o r r e l a t o r / dem o d u la t o r , the b i na r y o u t p u t sig n al lev e ls o f th e f r eq uen c y dis c r i mina t o r ar e alwa ys cen t er e d o n zer o . th e r efo r e , t h e slicer t h r e sh old l e vel ca n b e f i xe d a t z e r o a n d t h e de m o d u l a to r p e r f or manc e i s i n d e p e nd e n t of t h e r u n - l e ng t h c o nst r ai n t s of t h e t r ans m it d a t a bit st re am . t h i s re su lt s i n ro bu st d a t a re c o ve r y , which do es n o t suf f er f r o m t h e classic b a s e li ne wa nder p r ob lem s t h a t exist in t h e m o r e t r adi t io na l fsk demo d u l a t o rs. f r e q u e nc y e r rors are re move d by an i n te r n a l a f c l o op t h a t m e asur es t h e a v era g e if f r e q uen c y a t t h e l i mi t e r o u t p u t and a p p l i e s a f r eq u e n c y co rr ecti o n v a l u e t o th e f r a c ti o n al-n syn t h e sizer . t h is lo o p s h o u ld b e ac ti va t e d w h en the f r eq uen c y er r o rs a r e g r e a t e r t h a n a p p r o x ima t e l y 40% o f t h e t r an smi t f r eq u e n c y d e vi a t i o n (see t h e a f c s e cti o n ) . dat a sy nch r onizer an o v ers a m p le d dig i t a l pll is us e d t o r e sy n c hr o n ize t h e r e cei v ed b i t s t r e a m t o a lo cal c l o c k. th e o v ers a m p led c l o c k ra te o f th e p l l (c d r _ c l k ) m u s t be se t a t 32 tim e s th e da ta ra t e . s e e t h e n o t e s for t h e reg i ster 3re ce i v er c l o c k r e g i st er s e c t io n fo r a def i ni t i on o f h o w to p r o g r a m. th e clo c k r e co ver y p ll can acco mm o d a t e f r eq uenc y er r o rs o f u p t o 2% . fsk correla t o r register settings t o enab le t h e fs k co r r e l a t o r /dem o d u l a t o r , b i t s r4_d b(5:4) s h o u ld b e set t o [01]. t o ac hieve best p e r f o r m a n c e , t h e ba n d w i d t h o f th e fs k co rr e l a t o r m u s t be o p ti mi z e d f o r th e sp e c if ic de vi a t ion f r e q uen c y t h a t is us e d b y t h e fs k t r a n smi t t e r . the dis c r i mi na to r b w is co n t r o l l e d in reg i st er 6 b y r6_d b( 4:13) a n d is def i n e d as ) 10 800 /( ) _ ( _ 3 = k clk demod bw tor discrimina wher e: de mod _ c l k i s as def i n e d in t h e reg i st er 3 re ce i v er c l o c k regist er sec t io n, n o t e 2. k = ro u n d (200 e3/ fsk d e v i a t io n ) t o o p tim i ze t h e co ef f i cien ts o f th e fs k co r r e l a t o r , tw o addi tio n al b i ts, r6_d b14 an d r6_d b29, m u s t b e as sig n e d . th e val u e o f t h es e b i ts dep e n d s on w h et h e r k (as def i n e d abo v e) is o dd o r e v en. thes e b i ts a r e assig n e d acco r d in g to t a b l e 7 a n d ta b l e 8 . table 7. whe n k is eve n k k / 2 r 6 _ d b 1 4 r 6 _ d b 2 9 e v e n e v e n 0 0 e v e n o d d 0 1 table 8. whe n k is od d k (k + 1 ) /2 r6_db14 r6_db29 o d d e v e n 1 0 o d d o d d 1 1 pos tdemo dul ator b a n d w i d t h r e gis t er se ttings the 3 db b a n d wi d t h o f t h e p o st de m o d u l a t o r f i l t er is co n t r o l l e d b y b i ts r4_ d b ( 6 :15) a n d is gi v e n b y clk demod f bwsetting demod post cutoff _ 2 2 _ _ 10 = w h er e f cu to ff is t h e t a rg et 3 db b a ndwi d t h i n h z o f t h e p o s t de m o d u l a to r f i l t er . this s h o u ld typ i cal l y b e s e t t o 0.75 t i mes th e da ta ra t e (d r ) . s o me s a m p le s e t t in gs f o r the fs k co r r e l a t o r /dem o d u l a t o r a r e de mod _ c l k = 5 mh z dr = 9.6 k b ps f dev = 20 kh z ther efo r e , f cuto ff = 0.75 9.6 10 3 hz p o s t _d emo d _b w = 2 11 7.2 10 3 hz / ( 5 m h z ) p o s t _d emo d _b w = ro u n d (9.2 6) = 9 an d k = ro u n d (200 kh z)/20 kh z) = 10 dis c ri m i n a t o r_b w = (5 mh z 10)/(800 10 3 ) = 62.5 = 63 (r o u n d ed to n e a r es t in teg e r) table 9. setting name register addre ss value p o st_d e m o d _ b w r 4 _ d b ( 6 : 1 5 ) 0 x 0 9 discriminator b w r6_db(4:13) 0x3f dot product r6_db14 0 rx data invert r6_db29 0
prelim inary technical data adf7020 r e v. pr h | pa g e 19 o f 40 linear fsk demo dula tor a b l o c k d i a g ram o f th e lin e a r fs k d e m o d u la to r is s h o w n in f i gur e 17. av e raging filter en velope de te ctor slicer frequency if level i q limiter 7 mux 1 adc rssi output linear discriminator db(6:15) frequency readback and afc loop rx data 01975-p r g-017 f i g u re 17. bl ock d i ag r a m of f r equ e nc y m e as ure m ent sy s t em and ask . o o k/ li ne ar fsk dem o dula t o r this m e t h o d o f f r eq uen c y demo d u l a tion is us ef u l wh en v e r y shor t pre a mbl e l e ng t h i s re qu i r e d a n d t h e s y ste m proto c o l c a n n ot s u pp or t t h e ove r h e a d of t h e s e tt l i ng t i me of t h e i n te r n a l f eed back af c lo o p s e t t lin g . a dig i t a l f r e q ue n c y dis c r i min a to r p r o v ides a n ou t p ut sig n a l t h a t i s l i ne ar ly prop or t i on a l to t h e f r e q u e nc y of t h e l i m i t e r output s . the dis c r i mi na to r o u t p u t is t h e n f i l t er e d an d a v era g e d usin g a co m b i n e d a v erag in g f i l t er an d e n v e l op e de t e c t or . th e de mo d u - la te d f s k da t a i s r e co ver e d b y t h r e sh old - dete c t in g t h e o u t p u t of t h e a v era g i n g f i lt er , as s h own i n f i gur e 17. i n t h i s m o de , t h e sl i c e r output s h ow n i n f i g u re 1 7 i s route d to t h e d a t a s y nch r o- n i zer p ll f o r c l o c k sy n c hr o n iza t io n . t o en ab le th e lin e a r fs k demo d u la t o r , s e t b i ts r4_d b(4: 5) t o [00]. the 3 db b a n d wi d t h o f t h e p o s t de m o d u l a t i on f i l t er is s e t i n t h e s a me wa y a s t h e fs k co r r e l a t o r / d emo d u l a t o r , w h ich is s e t in r4_db(6:15) a n d is def i n e d as clk demod f setting bw demod post cutoff _ 2 2 _ _ _ 10 = wher e: f cuto ff is t h e ta r g et 3 db bandwid t h in h z o f the pos t d e m o d u la t o r f i l t e r . de mod _ c l k i s as def i n e d in t h e reg i s t er 3 re ce i v er c l o c k regist er sec t io n, n o t e 2. ask/ oo k op e r ation a s k/o o k de mo d u l a t i on is ac t i va te d b y s e t t in g bi ts r4_d b(4:5) t o [10]. dig i t a l f i lter in g a n d e n velo p e de te c t in g t h e dig i t i ze d rs s i in p u t v i a m ux 1, as sh o w n i n f i gur e 17, p e r f o r m a s k/o o k d e m o d u la ti o n . t h e ba n d w i d t h o f th e d i g i tal f i l t e r m u s t b e o p timize d t o r e m o v e an y exces s n o is e wi t h o u t ca usin g is i in t h e re c e ive d a s k / o o k s i g n a l . the 3 db b a n d wi d t h o f t h is f i l t er is typ i ca l l y s e t a t a p p r o x i- ma te l y 0.75 t i mes t h e us er da t a ra t e and is as sig n e d b y r4 _d b(6:15) as p o s t _d emo d _b w_s e tti n g = demod_clk f cutoff 2 2 10 wher e f cu to ff is t h e t a rg et 3 db b a ndwi d t h i n h z o f t h e pos t d e m o d u la t o r f i l t e r . afc section the ad f7020 su p p o r ts a r e al-t im e afc lo o p , w h ic h is us ed t o r e m o v e f r e q uenc y er r o rs t h a t can a r is e d u e t o misma t ch es b e tw e e n t h e t r an smi t and r e ceiv e cr ys t a ls. this us es t h e f r e q uen c y dis c r i mina to r b l o c k, as des c r i b e d in t h e l i n e a r f s k d e mo d u l a tor s e c t i o n ( s e e f i g u re 1 7 ) . the di s c r i mi na tor ou tpu t is f i l t er e d and a v era g e d t o r e m o v e t h e fsk f r e q uen c y mo d u l a t i o n u s i ng a c o mbi n e d a v e r ag i n g f i lte r an d e n vel o p e d e te c t or . i n f s k mo d e , t h e output of t h e e n v e l o p e d e t e c t or p r o v ides a n e s t i ma t e o f t h e a v er a g e if f r e q uen c y . t w o me t h o d s of a f c , e x te r n a l and i n te r n a l , are su pp or te d on th e ad f7020 (in fs k m o de o n l y ). external afc the us er r e ads bac k t h e f r e q ue n c y info r m a t ion t h r o ug h t h e ad f7020 s e r i al p o r t a n d a p p l ies a f r eq uen c y co r r ec tio n val u e t o t h e f r ac t i o n al-n syn t h e sizer s n divider . t h e f r eq ue n c y in f o rm a t i o n i s ob ta in ed b y r e a d in g th e 16- b i t si gn e d a f c_r e ad ba ck , a s d e scri be d i n t h e r e a d ba c k f o rm a t s e c t io n, and a p plyin g t h e fol l o w in g fo r m u l a: freq_r b [h z ] = ( afc_read b a ck de mo d _ c l k )/ 2 15 n o t e tha t wh ile th e a f c_r e adb a ck v a l u e is a sig n e d n u m b er , u n d e r nor m a l o p e r a t i n g c o nd it i o ns it i s p o s i t i ve . i n t h e ab s e nc e o f f r e q uen c y er r o rs, t h e freq_ r b val u e is e q u a l t o t h e if f r eq uen c y o f 200 kh z. inter n al afc the ad f7020 su p p o r ts a r e al-t im e in ter n al a u to ma tic f r eq uen c y co n t rol lo o p . i n this m o de , a n in ter n al co n t r o l lo o p a u t o ma t i cal l y mo ni t o rs t h e f r e q uen c y er r o r a n d ad j u s t s t h e syn t h e sizer n divider usin g an in t e r n al p i con t r o l lo o p . the in t e r n al af c co n t r o l lo o p p a ra m e ters a r e co n t r o l l ed in reg i st er 11. th e in t e r n a l afc lo o p is ac t i va t e d b y s e t t in g r11_d b 20 t o 1. a s c alin g co ef f i cien t m u s t als o be en t e r e d , b a s e d o n t h e cr yst a l f r e q uen c y in us e . this is s e t u p in r11_d b (4:19) a n d sh o u ld be c a lc u l a t e d usin g afc_s c a l i n g_ co eff i c i en t = (500 2 24 )/ xt a l ther efo r e , usin g a 10 mh z xt al yie l ds an afc s c ali n g co ef f i cien t o f 839.
adf7020 preliminary technical data rev. prh | page 20 of 40 maximum afc range the maximum afc frequency range is 100 khz. this is set by the maximum if filter bandwidth of 200 khz. using the minimum if filter bandwidth of 100 khz, the afc range is 50 khz. when afc errors have been removed using either the internal or external afc, further improvement in the receivers sensi- tivity can be obtained by reducing the if filter bandwidth using bits r1_db(22:23). automatic sync word recognition the adf7020 also supports automatic detection of the sync or id fields. to activate this mode, the sync (or id) word must be preprogrammed into the adf7020. in receive mode, this preprogrammed word is compared to the received bit stream and, when a valid match is identified, the external pin int/lock is asserted by the adf7020. this feature can be used to alert the microprocessor that a valid channel has been detected. it relaxes the computational requirements of the microprocessor and reduces the overall power consumption. the int/lock is automatically de- asserted again after nine data clock cycles. the automatic sync/id word detection feature is enabled by selecting demod mode 2 or 3 in the demodulator setup register. do this by setting r4_db(25:23) = [010] or [011]. bits r5_db(4:5) are used to set the length of the sync/id word, which can be either 12, 16, 20, or 24 bits long. the transmitter must transmit the msb of the sync byte first and the lsb last to ensure proper alignment in the receiver sync byte detection hardware. for systems using fec, an error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. the error tolerance value is assigned in r5_db(6:7).
prelim inary technical data adf7020 r e v. pr h | pa g e 21 o f 40 appli c ations section lna/pa matching the ad f7020 exhi b i ts o p t i m u m p e r f o r ma n c e in t e r m s o f s e ns it i v it y , t r a n s m it p o w e r , a n d c u r r e n t c o ns u m pt i o n on l y i f i t s rf in p u t an d ou t p u t p o r t s a r e p r o p erly ma t c he d t o t h e an t e nna im p e dan c e . f o r cos t -s en s i ti v e a p p l ica t io n s , the ad f7020 is e q ui p p e d wi t h an in t e r n al rx/tx swi t c h , w h ic h facili t a t e s t h e u s e of a s i m p l e c ombi n e d p a ss i v e p a / l n a m a t c h i ng ne t w or k . al t e r n a t i v e l y , a n ext e r n al rx/t x swi t ch s u c h as th e analog de vices ad g91 9 ca n be us e d , w h ic h yie l ds a s l ig h t l y im p r o v ed re c e ive r s e ns i t i v i t y a n d l o we r t r ans m itte r p o we r c o nsu m pt i o n . extern al rx/tx switch f i gur e 18 s h o w s a co nf igura t ion usin g a n ext e r n al rx/tx s w i t ch. t h is co nf igura t io n al lo ws a n indep e n d en t o p t i m i za tio n o f th e ma tch i n g and f i l t er n e tw o r k in t h e t r an smi t an d r e cei v e p a t h , a n d is, t h er efo r e, m o r e f l exi b le and les s dif f i c u l t t o desig n t h an t h e co nf igur a t ion usin g t h e in t e r n a l rx/tx s w i t ch. th e p a is b i ase d thr o ugh ind u c t o r l1, while c1 b l o c ks dc c u r r en t. b o th e l emen t s , l1 a n d c1, als o fo r m t h e ma t c hin g n e tw o r k, w h ich t r a n sfo r m s t h e s o ur ce im p e dan c e in t o t h e o p t i m u m p a lo ad im p e dan c e , z op t _p a. 01975-p rg-018 pa lna pa_out rfin rfinb v bat l1 adf7020 adg919 optional bpf (saw) optional lpf l a c a c b z in _rfin z opt _pa z in _rfin a ntenn a rx/tx ? select f i g u re 18. a d f7 02 0 w i t h e x te rna l r x / t x swit ch z op t _p a dep e nds o n va r i o us fac t o r s s u c h as t h e r e q u ir e d o u t p u t p o w e r , t h e f r e q uen c y ra n g e , t h e s u p p ly v o l t a g e r a n g e , an d t h e t e m p era t ur e ra ng e . s e le c t ing a n a p p r o p r i a t e z op t _p a h e l p s t o mini mi ze t h e tx c u r r en t co n s um p t ion in t h e a p plica t io n. this d a t a s h e e t c o nt a i n s a nu m b e r o f z op t _p a val u es fo r r e p r es en t a - t i ve c o nd it i o ns . u n d e r c e r t ai n c o nd it i o n s , howe ve r , it i s r e co mme n d e d to ob t a i n a su i t able z op t _ p a v a lu e by me ans of a lo ad-p u l l m e as u r em en t. d u e t o t h e dif f er en t i al ln a i n pu t, t h e ln a ma tchin g n e tw o r k m u s t be desig n e d t o p r o v ide bo t h a sin g le-en d e d t o dif f er en t i al co n v ersio n an d a co m p lex co n j uga t e i m p e dan c e ma t c h. th e n e t w o r k wi th t h e lo w e s t co m p o n en t co un t th a t ca n s a ti s f y th e s e r e q u ir em e n ts is t h e co nf igur a t ion sh o w n in f i gu r e 18, w h ich c o ns i s t s of t w o c a p a c i tor s a n d one i n d u c t or . a f i r s t - ord e r i m p l em en ta ti o n o f th e m a t c h i n g n e t w o r k ca n b e o b ta in ed b y u n d e r s t a nd i n g t h e ar r a nge m e n t a s t w o l- t y p e m a tch i ng n e tw o r ks in a b a ck-t o - b a ck co nf igura t io n. d u e t o t h e a s y m me t r y of t h e ne t w or k w i t h re sp e c t to g r ou n d , a c o m p ro- mis e b e t w e e n t h e i n p u t r e f l e c t i o n co ef f i cien t and t h e maxi m u m dif f er en t i al sig n al swin g a t t h e l n a i n p u t m u s t b e est a b l ish e d . the us e o f a p p r o p r i a t e ca d s o f t wa r e is s t r o n g ly r e co mm e n de d f o r th i s o p ti m i za ti o n . d e p e n d in g on t h e an te nna conf igur a t io n, t h e u s e r mig h t ne e d a ha r m o n ic f i l t er a t t h e p a o u t p u t t o s a t i sf y t h e sp ur io us emis sio n r e q u ir em e n t o f t h e a p plicab le go v e r n m e n t r e gu la t i on s. th e ha r m o n ic f i l t er ca n b e im ple m e n te d i n va r i o us wa y s , such as a discr e t e l c -f il t e r . die l ec tr ic lo w - p a s s f i l t er co m p o n en ts s u c h as th e lfl18924m t c 1a052 (f o r o p era t ion in the 915 mh z b a n d ) , o r lfl18869mt c 2a160 (f o r o p era t ion in the 868 mh z b a n d ) , bo th b y m u ra t a m f g . c o ., l t d . , r e p r e s e n t a n a t tra c ti v e al t e rn a t i v e t o dis c r e t e desig n s. th e imm u ni ty o f th e ad f7020 t o s t r o n g out - of - b an d i n t e r f e r e n c e c a n b e i m prove d by a d d i ng a b a n d - p a s s f i l t er in t h e rx p a th. a p a r t f r o m discr e t e design s, sa w o r d i e l ectri c f i l t e r co m p o n en t s s u c h a s t h e safch869mam0t00b0s, safch915mal0 n 00b0s, d c fb2869mle j a a - t t 1, o r d c fb3915mld j a a - t t 1, al l b y m u r a t a mf g . c o . , l t d. , are wel l s u i te d for t h i s pu r p o s e. inter n al rx/tx switch f i gur e 19 s h o w s th e ad f7020 in a co nf igur a t ion w h er e t h e in t e r n a l rx/ t x sw i t ch is us e d w i t h a com b i n e d ln a / p a m a tch i ng ne t w o r k . d e p e nd i n g o n t h e a p pl i c a t i o n , t h e sl i g h t p e r f o r ma n c e de g r ada t io n ca us e d b y t h e in ter n al rx/tx s w i t ch mig h t b e accept a b le , al lo win g t h e us er t o t a k e ad van t a g e o f t h e c o st - s av i n g p o t e n t i a l of t h i s s o lut i on . t h e d e s i g n of t h e c ombi n e d m a tc h i ng ne t w or k m u st c o m p e n s a te f o r t h e r e ac t a n c e p r es e n t e d b y t h e net w o r ks i n t h e tx a n d t h e rx p a t h s, t a kin g t h e s t a t e o f t h e rx/ t x s w i t ch in t o co n s idera t io n. 01975-p r g-019 pa lna pa_out rfin rfinb v bat l1 adf7020 optional bpf or lpf l a c a c1 c b z in _rfin z opt _pa z in _rfin antenna f i g u re 19. a d f7 02 0 w i t h int e rn al r x /t x switch the p r o c e d ur e t y p i cal l y r e q u ir es s e v e ral i t era t ion s un t i l an accep t ab le co m p r o mis e has been r e ac hed . the succes s f u l i m pl e m e n t a t i on of a c ombi n e d l n a / p a m a tch i ng ne t w or k f o r th e ad f7020 is cr i t ical l y dep e nden t on t h e a v a i la b i l i ty o f a n
adf7020 prelim inary technical data r e v. pr h | pa g e 22 o f 40 acc u ra t e e l e c t r ical m o de l fo r t h e pc b o a r d . i n t h is co n t ext, t h e us e o f a sui t ab le cad p a ck a g e i s st r o n g ly r e co mmende d . t o a v o i d t h is ef f o r t , th e r e f e r e n c e desig n p r o v ide d f o r th e ad f7020 rf m o d u le can be use d . a s wi t h t h e ext e r n al rx/t x swi t c h , a n addi tio n a l lp f o r b p f m i gh t b e r e q u ir ed t o s u p p r e s s ha r m o n ics in t h e tra n sm i t s p e c t r um o r t o i m p r o v e t h e r e si l i en c e o f t h e r e c e i v er a g a i ns t out - of - b an d i n t e r f e r e r s . transmi t protoc ol a n d c o di ng consi d era t io ns 01975-p rg-042 preamble sync word id field data field crc f i g u re 20. t y pic a l f o r m at of a t r ans m i t p r o t ocol a dc-f r e e p r e a m b le p a t t er n is r e co mme n d e d fo r fs k/as k/ o o k d e mo d u l a t i on . t h e re c o m m e n d e d pre a mbl e p a tte r n i s a dc-f r e e p a t t e r n s u c h as a 10101 010 p a t t e r n . p r ea m b le p a t t er ns wi t h lo n g er r u n-len g th co ns tra i n t s s u ch as 1100 1100. ca n als o b e us e d . h o w e ver , t h is r e su l t s in a lo n g er sy n c hr o n iz a t ion t i me of t h e re c e ive d bit st re a m i n t h e re c e ive r . m a n c h e s t er co din g can b e us e d fo r t h e en t i r e t r a n smi t p r o t o c ol. h o w e v e r , t h e r e ma ini n g f i e l ds t h a t fol l o w t h e pr e a m b le he ader do n o t ha v e t o u s e dc-f r e e co ding. f o r th es e f i e l ds, th e ad f7020 ca n acco mm o d a t e c o din g s c h e m e s wi th a r u n-len g th o f u p t o 6 bit s w i t h out a n y p e r f or m a nc e d e g r a d a t i o n . i f lo n g er r u n-len g th co din g m u s t b e s u p p o r t e d , th e ad f7020 has s e veral o t h e r fe a t ur es t h a t c a n b e ac t i va t e d . th e s e i n v o lv e a r a n g e o f p r o g r a mmable o p t i on s t h a t a l lo w t h e e n velop e de te c t or o u t p u t t o b e f r o z en a f t e r p r eam b le acq u isi t io n. image rejection calibration the ima g e c h ann e l in this r e c e iv er , wi th a n if a t 200 kh z, is a t ?200 kh z o r +4 00 kh z b e lo w th e desir e d sig n a l . th e p o l y p h as e f i l t er r e j e c t s t h is ima g e w i t h an asymm e t r ic f r e q uen c y r e sp o n s e . the ima g e r e je c t io n p e r f o r ma nce o f t h e r e ceiv e r is dep e n d e n t o n h o w wel l ma tche d i n am pli t ude t h e i and q sig n a l s a r e, a n d h o w p e r f e c t t h e q u adr a t u r e is b e tw e e n t h em, t h a t is, h o w clos e to 9 0 a p ar t t h e y are. the u n c a l i b r a t e d i m age re j e c t i o n p e r f or m- a n c e is a p p r o x im a t e l y 30 db . h o w e v e r , i t is p o ssi b l e t o im p r o v e on t h i s p e r f or m a nc e by a d ju st i n g t h e i / q ph a s e / g a i n a d ju st bit s in reg i st er 10, r e su l t in g i n an i m a g e r e j e c t ion o f a p p r o x ima t e l y 45 db . b i ts r10_d b (24 : 27) ad j u s t t h e re l a ti v e p h as e o f th e sig n al a n d b i ts r10_db(16:20) ad j ust th e r e la t i v e am pli t ude (s ee f i gur e 20). polyphase filter lo q lo i gain phase 01975-p r g-020 lna mixers f i g u re 20. phas e / g a in adjus t ment on a d f70 20 device programming after initial power-up b a sic mo de is t h e mini m u m n u m b er o f wr i t e s e q u e n ces t o p o w e r u p t h e de vice . en han c e d m o de us es t h e addi t i onal f e a t ur es o f th e ad f7020 t o ta ilo r th e p a r t t o a p a r t ic u l a r a p plic a t ion such as s e t t i n g u p a syn c b y te s e q u e n ce o r doin g a u t o ma tic f r eq u e n c y co n t r o l . the s a m p le s e t t in g is fo r t h e fol l o w in g s e t u p: frf = 915 mh z, fs k, dr = 9.868 k b ps, i cp = 1.44 ma f dev = 50 kh z , xt a l = 10 mh z, c o r r ela t o r/dem od u l a t o r
prelim inary technical data adf7020 r e v. pr h | pa g e 23 o f 40 01975-p r g-023 write to r0 write to r1 write to r3 register write write to r4 write to r5 write to r6 write to r9 write to r10 write to r11 program frequency set up oscillator and if filter set up rx clocks primary function set up demod set up sync byte sequence set up rx mode set up agc parameters and lna/gain filter set up i/q gain/phase adjust set up afc parameters 0x0000 0x0000 0x0000 example setting 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 01975-p r g-021 write to r0 write to r1 write to r2 register write program frequency set up oscillator and if filter set up modulation parameters primary function 0x72dc 0000 0x86 9011 0x8022 6012 example setting f i g u re 21. bas i c m o de t x 01975-p r g-022 write to r0 write to r1 write to r3 register write write to r4 write to r6 program frequency set up oscillator and if filter set up rx clocks primary function set up demod set up rx mode 0x7adb d710 0x86 9011 0x64 2053 example setting 0x0194 0x2c82 0326 f i u re 23. e nhan c e d m o d e x f i u re 22. as i c m o de x 01975-p r g-024 write to r0 register write change frequency and change mode to rx primary function 0x0000 example setting f i gure 2 4 . change mo de f r om t x t o rx
adf7020 prelim inary technical data r e v. pr h | pa g e 24 o f 40 serial interface the s e r i al in ter f ace al lo ws t h e u s e r t o p r og ra m t h e e l e v e n 32- b i t r e g i s t ers usin g a 3-wir e in t e r f ace (sclk, s d a t a, a n d s l e). i t co n s is ts o f a leve l s h if t e r , 32-b i t s h if t r e g i st er and e l e v en la t c h e s. sig n a l s sh o u l d b e cmos com p a t ib le . th e s e r i a l in t e r f ace is p o w e r e d b y th e r e gula t o r , an d , t h er ef o r e , is inac ti v e w h en ce is lo w . da t a is c l o c k e d in t o t h e r e gist er , ms b f i r s t, o n t h e r i sin g e d g e o f ea c h c l oc k (sc l k ) . da t a i s tra n sf e r r e d t o o n e o f e l ev en la t c h e s o n t h e r i sin g e d ge o f s l e. the dest ina t io n la t c h is det e r m i n e d b y t h e val u e o f t h e fo ur co n t r o l b i ts (c4 t o c1). th e s e a r e t h e bo t t o m f o ur ls bs, d b 3 t o d b 0, as sh o w n in t h e tim i n g dia g ram in f i gur e 2. d a t a can also be r e ad back o n t h e s r ead p i n. readback format the r e adb a ck op era t ion is ini t i a t e d b y wr i t in g a va lid con t r o l w o r d t o t h e r e ad b a ck r e g i s t er and s e t t in g t h e re ad b a ck- e na b l e b i t (r7_d b 8 = 1). th e r e ad back can beg i n a f t e r th e co n t r o l w o r d has be e n l a t c h e d wi t h t h e s l e sig n al . s l e m u s t be k e p t high while t h e da ta is bein g r e ad o u t. e a c h ac ti ve edg e a t t h e sclk p i n c l o c ks th e r e ad back w o r d o u t s u ccessi v e l y a t t h e s r ea d p i n , a s s h o w n in f i g u r e 25, s t a r ti n g wi th th e m s b f i r s t . the da t a a p p e a r in g a t t h e f i rs t clo c k c y cle fol l o w in g t h e l a t c h o p era t ion m ust b e ig n o r e d . afc re ad back t h e afc r e ad b a c k is valid o n l y d u r i n g the r e cep t io n o f fs k s i g n a l s w i th e i th e r th e l i n e a r o r c o rr e l a t o r d e m o d u la t o r a c t i v e . the afc r e ad b a ck val u e is fo r m a t t e d as a sig n e d 16- b i t in t e g e r co m p r i sed o f b i ts r v 1 t o r v 16, a n d is scale d ac co r d in g t o t h e fol l o w ing fo r m u l a: freq_r b [h z ] = ( afc_read b a ck dem o d _ cl k )/ 2 15 i n t h e a b s e n c e of f r e q uen c y er r o rs, t h e freq_r b val u e is e q u a l t o th e if f r eq uen c y o f 200 kh z. n o t e tha t , f o r the afc r e ad back to y i eld a va lid resu l t , t h e do w n - c o n ver t e d i n p u t sig n a l m u st n o t fal l o u tside t h e b a ndwi d t h o f t h e a n alogue if f i l t er . a t lo w-in p u t sig n al lev e ls, the va r i a t ion in the r e ad back val u e ca n be im p r o v e d b y a v era g in g. rssi r e a d b a ck the rss i r e ad b a ck o p er a t io n y i e l ds valid r e s u l t s in rx m o de wi t h a s k o r fs k signals. t h e f o r m a t o f th e r e ad back w o r d is s h own in f i gur e 25. i t is co m p r i s e d o f the rss i lev e l inf o r m a - t i o n (b i t s r v 1 to r v 7), t h e c u r r en t f i l t er ga i n (fg1, fg2), a n d t h e c u r r en t l n a ga in (l g1, lg2) s e t t i n g. the f i l t er a n d l n a ga in a r e co ded in acco rdan ce wi th t h e def i ni t i on s in reg i s t er 9. w i t h t h e re c e pt i o n of a s k mo du l a te d s i g n a l s , ave r ag i n g of t h e m e as ur e d rs s i val u es im p r o v es acc u rac y . th e i n p u t p o w e r ca n b e calc u l a t e d f r o m t h e rss i r e ad b a ck val u e as o u t l in e d i n t h e rss i /a g c s e c t i o n. ba ttery voltage adc i n/tempera t u r e sensor re adb ack the b a t t e r y v o l t a g e is m e as ur e d a t p i n vd d4. th e r e ad b a ck info r m a t io n is c o n t a i ne d i n bi ts r v 1 t o r v 7. this a l s o a p plies fo r t h e r e ad b a ck o f t h e v o l t a g e a t t h e ad ci n pin and t h e t e m p era t ur e s e ns o r . f r o m t h e r e ad b a ck info r m a t io n, t h e b a t t er y o r ad ci n v o l t ag e ca n b e det e r m in e d usin g v ba t t e r y = ( ba tt er y_v o l t a g e_read bac k )/21.1 v ad cin = ( ad cin_v o l t a g e_re ad bac k )/42.1 silicon revisi on readback the si lico n re visio n r e ad b a ck wo r d is va lid w i t h o u t s e tt in g an y o t h e r r e g i s t ers, es p e c i al ly dir e c t ly a f t e r p o w e r - u p . the si lico n r e visio n w o r d is co ded wi th f o ur q u a r t e ts in b c d f o r m a t . th e p r o d uc t co de (pc) is co de d wi t h tw o qua r t e ts e x t e ndin g f r o m b i ts r v 9 t o r v 16. t h e r e visio n co de (r v) is co ded wi th tw o qu ar te t s e x te ndi n g f r om bi t s r v 1 to r v 8 . t h e pro d u c t c o de s h o u ld r e ad back as pc = #20 h. t h e c u r r en t r e visio n co de s h o u ld r e ad as r c = #30h. filter cali brat ion readback the f i l t er cal i b r a t io n r e ad b a ck w o r d is co n t a i ne d i n b i ts r v 1 to r v 8, an d is fo r di a g n o st ic p u r p os es o n ly . u s in g t h e a u t o ma t i c f i l t er calib r a t io n f u n c t i on, accessi b l e t h r o ug h r e g i s t er 6, is r e co mme n d e d . 01975-p r g-025 readback mode afc readback db15 rv16 x x rv16 0 rssi readback battery voltage/adcin/ temp. sensor readback silicon revision filter cal readback readback value db14 rv15 x x rv15 0 db13 rv14 x x rv14 0 db12 rv13 x x rv13 0 db11 rv12 x x rv12 0 db10 rv11 lg2 x rv11 0 db9 rv10 lg1 x rv10 0 db8 rv9 fg2 x rv9 0 db7 rv8 fg1 x rv8 rv8 db6 rv7 rv7 rv7 rv7 rv7 db5 rv6 rv6 rv6 rv6 rv6 db4 rv5 rv5 rv5 rv5 rv5 db3 rv4 rv4 rv4 rv4 rv4 db2 rv3 rv3 rv3 rv3 rv3 db1 rv2 rv2 rv2 rv2 rv2 db0 rv1 rv1 rv1 rv1 rv1 f i gure 25. r e adb a c k v a lu e t a ble
prelim inary technical data adf7020 r e v. pr h | pa g e 25 o f 40 register 0n register tr1 transmit/ receive 0 transmit receive 1 m3 m2 m1 muxout 0 regulator ready (default) 0 r d i v i d e r o u t p u t 0 n divider output 0 digital lock detect 1 analog lock detect 1 three-state 1 pll test modes 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 - ? test modes ple1 pll enable 0 pll off 1 pll on 01975-p r g-026 n8 n7 n6 n5 n4 n3 n2 n1 n counter divide ratio 03 1 03 2 . . . 1 253 1 254 1 0 0 . . . 1 1 1 0 1 . . . . . . 1 1 1 1 0 1 1 1 . . . 1 0 1 1 1 . . . 1 0 1 1 1 . . . 1 0 0 1 1 . . . . . . 1 0 1 0 1 255 15-bit fractional-n 8-bit integer-n tx/rx pll e nable muxout address bits n5 n4 n8 m5 m6 m7 m8 m1 2 m1 3 m1 5 n1 n2 n3 m1 4 m9 m1 0 m1 1 m4 m3 tr1 ple1 m1 m3 m2 c2 (0 ) c1 (0 ) c3 (0 ) c4 (0 ) m1 m2 n7 n6 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 fractional divide ratio 4 5 6 . . . 32764 32765 32766 32767 m15 0 0 0 . . . 1 1 1 1 m14 0 0 0 . . . 1 1 1 1 m13 0 0 0 . . . 1 1 1 1 ... ... ... ... ... ... ... ... ... ... ... m3 1 1 1 . . . 1 1 1 1 m2 0 0 1 . . . 0 0 1 1 m1 0 1 0 . . . 0 1 0 1 f i g u re 26. notes : 1. t h e t x/r x bi t (r 0 _ d b 27) c o n f i g u r e s t h e pa r t i n t x or r x m o de a n d a l so c o n t r o l s t h e st a t e of t h e i n t e rn a l t x/r x swi t ch . 2. ) 2 ( 15 -n fractional integer-n r xtal f out + = .
adf7020 prelim inary technical data r e v. pr h | pa g e 26 o f 40 register 1oscillator/filter register r3 r2 r1 rf r counter divide ratio 0 0 . . . 1 1 2 . . . 7 1 0 . . . 1 0 1 . . . 1 x1 xtal osc 0 off 1o n va2 va1 frequency of operation 0 880 ?950 0 870 ?940 1 860 ?930 1 0 1 0 1 850 ?920 d1 xtal doubler 0 disable enabled 1 v1 vco band mhz 0 866? 940 1 433? 470 cp2 cp1 rset i cp (ma) 3.6k ? 0 0 0.3 0 1 0.9 1 0 1.5 1 1 2.1 vb4 vb3 vb2 vb1 vco bias current 0 0.5ma 0 1ma . 1 1 0 . 1 0 1 . 1 0 0 . 1 8ma ir2 ir1 filter bandwidth 0 100khz 0 150khz 1 200khz 1 0 1 0 1 not used cl4 cl3 cl2 cl1 clk out divide ratio 0 off 0 0 . . . 1 0 1 0 . . . 1 2 4 . . . 0 0 1 . . . 1 0 0 0 . . . 1 30 vco bias cp curre nt v c o band xosc e nable clockout divide address bits r counter xta l double r vc o adj us t if filter bw ir2 ir1 cl1 cl2 cl3 cl4 dd2 vb 1 vb 3 vb 4 va 1 va 2 vb 2 x1 v1 dd1 d1 r3 c2 (0 ) c1 (1 ) c3 (0 ) c4 (0 ) r1 r2 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 01975-p r g-027 f i g u re 27. notes : 1. s e t the vc o ad jus t bits ( r 1_ db( 20:21 ) t o 0 f o r nor mal o p era t io n. 2. ) 2 ( 15 -n fractional integer-n r xtal f out + = .
prelim inary technical data adf7020 r e v. pr h | pa g e 27 o f 40 register 2transm it modulati on regis t er (ask/ook mode) p6 0 0 0 0 . . 1 . . . . . . . 1 . . . . . . . 1 p2 x 0 0 1 . . 1 p1 x 0 1 0 . . 1 power amplifier output high level pa off ?16.0dbm ?16 + 0.45dbm ?16 + 0.90dbm . . 13dbm d6 x 0 0 0 0 . . 1 . . . . . . . . 1 d5 x x 0 0 . . . 1 d2 x x 0 0 1 . . 1 d1 x x 0 1 0 . . 1 power amplifier output low level ook mode pa off ? 16.0dbm ? 16 + 0.45dbm ? 16 + 0.90dbm . . 13dbm di1 0 1 txdata txdata modulation parameter power amplifier gfsk mod control inde x counte r tx data invert pa bias modulation scheme address bits pa e nable mute p a until lock pe1 0 1 power amplifier off on mp1 0 1 mute pa until lock detect high off on pa2 0 1 0 1 pa1 0 0 1 1 pa bias 5 a 7 a 9 a 11 a ic2 x ic1 x mc3 x mc2 x mc1 x s3 0 0 1 0 1 s2 0 0 0 1 1 modulation scheme fsk gfsk ask ook g - ook s1 0 1 0 1 1 01975-p r g-028 d9 d8 mc3 s3 p1 p2 p3 d1 d2 d4 d5 d6 d7 d3 p4 p5 p6 s2 s1 ic1 ic2 di1 pa 2 pa 1 c2 (1 ) c1 (0 ) c3 (0 ) c4 (0 ) pe1 mp 1 mc2 mc1 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 f i g u re 28. not e : 1. see t h e t r an smitt e r sec t ion f o r a de s c r i pt ion of h o w t h e p a bias a f f e c t s po w e r amplifier l e v e l . default lev e l is 9 a .
adf7020 prelim inary technical data r e v. pr h | pa g e 28 o f 40 register 2transm it modulation regis t er (fsk m o de) modulation parameter power amplifier gfsk mod control inde x counte r tx data invert pa bias modulation scheme address bits pa e nable mute p a until lock d9 d8 mc3 s3 p1 p2 p3 d1 d2 d4 d5 d6 d7 d3 p4 p5 p6 s2 s1 ic1 ic2 di1 pa 2 pa 1 c2 (1 ) c1 (0 ) c3 (0 ) c4 (0 ) pe1 mp 1 mc2 mc1 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 di1 0 1 txdata txdata pa2 0 0 1 1 pa1 0 1 0 1 pa bias 5 a 7 a 9 a 11 a ic2 x ic1 x mc3 x mc2 x mc1 x d9 0 0 0 0 . 1 d3 0 0 0 0 . 1 .... .... .... .... .... .... .... d2 0 0 1 1 . 1 d1 0 1 0 1 . 1 for fsk mode, f deviation pll mode 1 f step 2 f step 3 f step . 511 f step p6 0 0 0 0 . . 1 . . . . . . . 1 . . . . . . . 1 p2 x 0 0 1 . . 1 p1 x 0 1 0 . . 1 power amplifier output level pa off ? 16.0dbm ? 16 + 0.45dbm ? 16 + 0.90dbm . . 13dbm pe1 0 1 power amplifier off on mp1 0 1 mute pa until lock detect high off on s3 0 0 0 0 1 s2 0 0 1 1 1 modulation scheme fsk gfsk ask ook g - ook s1 0 1 0 1 1 01975-p r g-029 f i g u re 29. not e s : 1. . 14 2 / pfd f step = p a bi a s d e fa u l t = 9 a .
prelim inary technical data adf7020 r e v. pr h | pa g e 29 o f 40 register 2transm it modulation regis t er (gfsk/g ook mode) modulation parameter power amplifier gfsk mod control inde x counte r tx data invert pa bias modulation scheme address bits pa e nable mute p a until lock d9 d8 mc3 s3 p1 p2 p3 d1 d2 d4 d5 d6 d7 d3 p4 p5 p6 s2 s1 ic1 ic2 di1 pa 2 pa 1 c2 (1 ) c1 (0 ) c3 (0 ) c4 (0 ) pe1 mp 1 mc2 mc1 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 di1 0 1 txdata txdata pa2 0 1 0 1 pa1 0 0 1 1 pa bias 5 a 7 a 9 a 11 a ic2 0 0 1 1 ic1 0 1 0 1 index_counter 16 32 64 128 d9 0 0 1 1 d8 0 1 0 1 gaussian ? ook mode bleed/buffer off output buffer on bleed current on bleed/buffer on 01975-p r g-030 mc3 0 0 . 1 mc2 0 0 . 1 gfsk_mod_control 0 1 . 7 mc1 0 1 . 1 d7 0 0 0 0 . 1 d3 0 0 0 0 . 1 ... ... ... ... ... ... ... d2 0 0 1 1 . 1 d1 0 1 0 1 . 1 divider_factor invalid 1 2 3 . 127 pe1 0 1 power amplifier off on mp1 0 1 mute pa until lock detect high off on s3 0 0 1 0 1 s2 0 0 0 1 1 modulation scheme fsk gfsk ask ook g - ook s1 0 1 0 1 1 p6 0 0 0 0 . . 1 . . . . . . . 1 . . . . . . . 1 p2 x 0 0 1 . . 1 p1 x 0 1 0 . . 1 power amplifier output level pa off ? 16.0dbm ? 16 + 0.45dbm ? 16 + 0.90dbm . . 13dbm f i g u re 30. not e s : 1. gfsk_ d e v ia tio n = (2 g f sk_m od _c on t r ol pfd )/2 12 . 2. dr = p f d/( i nde x_c o unte r divider_ f a c t or) . 3. p a bi a s d e fa u l t = 9 a .
adf7020 prelim inary technical data r e v. pr h | pa g e 30 o f 40 register 3receiver clock register fs8 0 0 . 1 1 fs7 0 0 . 1 1 fs3 0 0 . 1 1 ... ... ... ... ... ... fs2 0 1 . 1 1 fs1 1 0 . 0 1 cdr_clk_divide 1 2 . 254 255 bk2 0 0 1 bk1 0 1 x bbos_clk_divide 4 8 16 sk8 0 0 . 1 1 sk7 0 0 . 1 1 sk3 0 0 . 1 1 ... ... ... ... ... ... sk2 0 1 . 1 1 sk1 1 0 . 0 1 seq_clk_divide 1 2 . 254 255 ok2 0 0 1 1 ok1 0 1 0 1 demod_clk_divide 4 1 2 3 sequencer clock divide cdr clock divide bb offs e t clock div i de de mod clock div i de address bits sk 8 sk 7 fs1 fs2 fs3 fs4 fs8 sk 1 sk 3 sk 4 sk 5 sk 6 sk 2 fs5 fs6 fs7 ok2 ok1 c2 (1 ) c1 (1 ) c3 (0 ) c4 (0 ) bk1 bk2 ir2 ir1 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 01975-p r g-031 f i g u re 31. not e s : 1. b a s e band o ffse t clock fre q ue nc y ( b b o s_ c l k ) mus t be gre a t e r than 1 m h z and l e ss than 2 mh z , whe r e : divide clk bbos xtal clk bbos _ _ _ = 2. t h e dem o dula t o r c l ock (d e m od _cl k ) m u st be < 12 mhz f o r f s k a n d < 6 mh z f o r a s k , wh e r e: divide clk demod xtal clk demod _ _ _ = 3. d a ta /clock r e c o v e r y f r eq uen c y ( c d r _ clk ) sh o u l d be wi t h i n 2% of (32 da ta r a t e ), wh er e: divide clk cdr clk demod clk cdr _ _ _ _ = n o t e t h a t th i s m i g h t a f f e c t y o ur ch oi c e of xt al, dep e n d i n g on t h e de si r e d da ta r a t e . 4. t h e sequenc e r cloc k (seq _cl k ) sup p lies the cloc k t o the dig i tal r e c e iv e bloc k . i t shou ld be c l ose t o 100 khz f o r fsk and close t o 40 k h z f o r as k : divide clk seq xtal clk seq _ _ _ =
prelim inary technical data adf7020 r e v. pr h | pa g e 31 o f 40 register 4demodu lator setu p register demodulator lock setting postdemodulator bw de mod selec t de mod lock/ s y nc word match address bits dl8 dl7 dw3 dw4 dw5 dw6 dw1 0 dl1 dl3 dl4 dl5 dl6 dl2 dw7 dw8 dw9 dw2 dw1 c2 (0 ) c1 (0 ) c3 (1 ) c4 (0 ) ds 1 ds 2 lm2 lm1 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 ds2 0 0 1 1 ds1 0 1 0 1 demodulator type linear demodulator correlator/demodulator ask/ook invalid lm2 0 0 0 0 1 1 demod mode 0 1 2 3 4 5 lm1 0 0 1 1 0 1 demod lock/sync word match serial port control ? free running serial port control ? lock threshold sync word detect ? free running sync word detect ? lock threshold interrupt/lock pin locks threshold demod locked after dl8 ? dl1 bits int/lock pin ? ? output output input ? dl8 0 1 0 1 x dl8 dl7 0 0 0 . 1 1 dl8 0 0 0 . 1 1 dl3 0 0 0 . 1 1 ... ... ... ... ... ... ... dl2 0 0 1 . 1 1 dl1 0 1 0 . 0 1 lock_threshold_timeout 0 1 2 . 254 255 01975-p r g-032 mode5 only f i g u re 32. not e s : 1. t h e cut o ff f r eq uen c y o f t h e po st dem o d u la t o r fi lt er sh ou ld typi ca lly be 0.75 t i m e s t h e da t a r a t e . 2. d e modu la t o r modes 1, 3, 4, and 5 ar e modes tha t can be ac tiva t e d t o allow the adf7020 t o demodula t e da ta - e nc oding schem e s that ha v e run-l e n gth co ns traints gre a t e r than 7. 3. p o st_d emod_b w = 2 11 f cut o ff / demod _ clk . 4. f o r m o de 5, t h e t i m eout dela y t o lock t h r esh o l d = (l ock _ thr e s h old _ s e t t i n g)/s eq_cl k , wh e r e seq _clk i s de fi n e d i n t h e reg i st er 3 rec e iv er c l ock reg i st er sec t i o n .
adf7020 prelim inary technical data r e v. pr h | pa g e 32 o f 40 register 5sync b y te register pl2 0 0 1 1 pl1 0 1 0 1 sync byte length 12 bits 16 bits 20 bits 24 bits mt2 0 0 1 1 mt1 0 1 0 1 matching tolerance 0 errors 1 error 2 errors 3 errors sync byte sequence control bits syn c b y te length matching tole rance mt2 mt1 c2 (0 ) c1 (1 ) c3 (1 ) c4 (0 ) pl1 pl2 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 01975-p r g-033 f i g u re 33. not e s : 1. sync b y t e det e c t is enabl e d b y pr og r amming bits r4_ d b(25:23) t o [ 010 ] or [ 011] . 2. t h i s r e g i st er a llo w s a 28- bi t syn c b y t e s e q u en c e t o be st or ed i n t e rn a lly . if t h e syn c b y t e d e t e c t m o de i s se le c t ed , t h e n t h e in t/l o c k pin go e s high whe n the sync b y t e h a s been det e c t ed i n r x m o de . on c e t h e syn c w o r d det e c t si g n a l h a s g o n e h i gh , i t goe s lo w a g a i n a f t e r n i n e da t a bi t s . 3. t h e t r a n sm i t t e r m u st t x t h e m s b of t h e syn c b y t e fi rst a n d t h e lsb la st t o en su r e p r oper a l i g n m en t i n t h e r e c e i v er s y n c b y t e d e t e c t io n hard ware .
prelim inary technical data adf7020 r e v. pr h | pa g e 33 o f 40 register 6correlator/demodulator r e gister demod reset cdr reset discriminator bw if filter divider lna curre nt lna mode dot p r oduct rx data in ver t if filter cal m i xer linearity rx reset address bits fc4 fc3 fc7 td5 td6 td7 td8 lg1 li1 ml1 ca1 fc1 fc2 li2 td9 td10 dp 1 td4 td3 fc8 fc9 ri1 c2 (1 ) c1 (0 ) c3 (1 ) c4 (0 ) td1 td2 fc6 fc5 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 ri1 0 1 rxdata invert rxdata rxdata ca1 0 1 filter cal no cal calibrate ml1 0 1 mixer linearity default high dp1 0 1 dot product cross product dot product lg1 0 1 lna mode default reduced gain fc3 0 0 . . . . 1 fc1 1 0 . . . . 1 filter clock divide ratio 1 2 . . . . 511 fc2 0 1 . . . . 1 fc9 0 0 . . . . 1 fc6 0 0 . . . . 1 . . . . . . . . fc5 0 0 . . . . 1 fc4 0 0 . . . . 1 li2 0 li1 0 lna bias 800 a (default) 01975-p r g-034 f i g u re 34. not e s : 1. s e e t h e f s k c o rr ela t or/demodu l a t or s e c t ion f o r an exam ple of h o w t o det e rmin e r e g i st er set t i n g s . 2. nonad h erenc e t o c o r r el a t or pr ogramming gui d e l i nes r e sul t s in poor er s e ns it ivit y . 3. t h e fi lt er c l oc k i s u s ed t o ca li br a t e t h e if fi lt er . t h e fi lt er c l o c k di vi d e r a t i o sh ou ld be a d j u st ed so t h a t t h e fr eq uen c y i s 50 kh z. t h e f o r m u l a is xt al/fil ter_cl ock_divide. 4. t h e fi lt er sh ou ld be ca li br a t ed on ly wh en t h e cr y s t a l osci ll a t or i s set t l e d . t h e f i lt er ca li br a t i o n i s i n i t ia t e d ev er y t i m e b i t r 6 _d b19 i s set h i gh . 5. d isc rimi nat o r_bw = ( de mod_clk k )/(800 10 3 ). see t h e fsk c o rr ela t or/de m odula t or s e c t ion .
adf7020 prelim inary technical data r e v. pr h | pa g e 34 o f 40 register 7readback setup register ad1 ad2 rb1 rb2 rb3 db8 db7 db6 db5 db4 db3 db2 c2(1) c1(1) control bits db1 db0 c3(1) c4(0) readback select adc mode ad2 0 0 1 1 ad1 0 1 0 1 adc mode measure rssi battery voltage temp sensor to external pin rb2 0 0 1 1 rb1 0 1 0 1 readback mode afc word adc output filter cal silicon rev rb3 0 1 readback disabled enabled 01975-p r g-035 f i g u re 35. not e s : 1. rea d ba ck of t h e m e a s ur ed r ssi v a lue i s v a li d on ly i n r x m o de . rea d ba ck o f t h e ba t t er y v o lt a g e , t h e t e m p er a t ur e se n s or , a n d t h e v o l t a g e a t the e x t e r n al p i n is no t a v ail abl e in rx mode , if the a s k d e modul a t o r is ac tiv e or if a g c is enabl e d. 2. rea d ba ck of t h e a d c v a lue i s v a li d i n t x m o d e on ly i f t h e log a m p /r ssi h a s n o t been di sa bl ed t h r ough t h e po w e r - d o wn bi t s r 8 _d b1 0. t h e l o g amp/rssi sec t ion is a c t i v e per de fa ult u p on en a b li n g t x m o de . 3. rea d ba ck of t h e a f c w o r d i s v a li d i n r x m o d e on ly i f ei t h e r t h e li n e a r d e m o dula t o r or t h e c o rr e l a t or/dem odu l a t or i s a c t i v e . 4. s e e t h e r e a d ba ck f o rm a t sec t ion f o r m o re inf o r m a t ion.
prelim inary technical data adf7020 r e v. pr h | pa g e 35 o f 40 register 8power-down test register pd1 pd2 pd3 pd4 pd5 db8 db7 db6 db5 db4 db3 db2 c2(0) c1(0) control bits db1 db0 c3(0) c4(1) log amp/ rssi syn t h e nable vc o e nable lna/mix e r e nable filter e nable adc e nable de mod e nable inte rnal tx /rx s w itch e nable p a e nable rx mode pd7 db15 db14 db13 db12 db11 lr1 pd6 db10 db9 lr2 sw1 pd9 0 1 pa (rx mode) pa off pa on pd4 0 1 tx/rx switch default (on) off pd6 0 1 demod enable demod off demod on pd5 0 1 adc enable adc off adc on lr2 x x lr1 0 1 rssi mode rssi off rssi on pd4 0 1 filter enable filter off filter on pd3 0 1 lna/mixer enable lna/mixer off lna/mixer on ple1 (from reg 0) 0 0 0 0 1 pd2 0 0 1 1 x loop condition vco/pll off pll on vco on pll/vco on pll/vco on pd1 0 1 0 1 x 01975-p r g-036 f i g u re 36. not e s : 1. f o r a c o mbined ln a / p a ma t c h i ng net w ork , bit r8_ d b12 s h ould al wa ys be se t t o 0. t h is is the p o we r-up de f a ul t cond itio n. 2. i t is no t ne ces s a r y t o wr it e t o this r e gist e r und e r no r mal ope r a t i n g co nd itio ns.
adf7020 prelim inary technical data r e v. pr h | pa g e 36 o f 40 register 9agc register agc high threshold lna gain filter gain digital test iq agc s e arch gain control filter curre nt agc low threshold address bits fg2 fg1 gl5 gl6 gl7 gh1 gh5 gh6 gs1 gc1 lg1 lg2 gh7 gh2 gh3 gh4 gl4 gl3 c2 (0 ) c1 (1 ) c3 (0 ) c4 (1 ) gl1 gl2 fi1 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 fi1 0 1 filter current low high gs1 0 1 agc search auto agc hold setting gc1 0 1 gain control auto user fg2 0 0 1 1 fg1 0 1 0 1 filter gain 8 24 72 invalid lg2 0 0 1 1 lg1 0 1 0 1 lna gain 3 10 30 invalid gl3 0 0 0 1 . . . 1 1 1 gl1 1 0 1 0 . . . 1 0 1 agc low threshold 1 2 3 4 . . . 61 62 63 gl2 0 1 1 0 . . . 0 1 1 gl7 0 0 0 0 . . . 1 1 1 gl6 0 0 0 0 . . . 1 1 1 gl5 0 0 0 0 . . . 1 1 1 gl4 0 0 0 0 . . . 1 1 1 gh3 0 0 0 1 . . . 1 1 0 gh1 1 0 1 0 . . . 0 1 0 rssi level code 1 2 3 4 . . . 78 79 80 gh2 0 1 1 0 . . . 1 1 0 gh7 0 0 0 0 . . . 1 1 1 gh6 0 0 0 0 . . . 0 0 0 gh5 0 0 0 0 . . . 0 0 1 gh4 0 0 0 0 . . . 1 1 0 01975-p r g-037 f i g u re 37. not e s : 1. defa u l t a g c_l ow _ t hr es hold = 27, d e fa ult a g c_ high _t hr es hold = 76. s e e t h e r s si/a g c s e ct i o n f o r m o r e det a i l s . 2. a g c high and l o w s e ttings mus t be m o re than 30 apar t to e n sure cor r ec t o p e r a t io n. 3. ln a ga i n of 30 i s a v a i l a b le on ly i f ln a m o de , r 6 _d b15, i s set t o z e r o .
prelim inary technical data adf7020 r e v. pr h | pa g e 37 o f 40 register 10agc 2 register agc delay i/q gain adjust leak factor i/q phase adjust up /dow n r eser ved selec t i/q selec t i/q peak response address bits r1 siq1 ph 3 gl4 gl5 gl6 gl7 dh4 gc1 gc3 gc4 gc5 ud1 gc2 dh1 dh2 dh3 pr 4 pr 3 ph 4 siq2 c2 (1 ) c1 (0 ) c3 (0 ) c4 (1 ) pr 1 pr 2 ph 2 ph 1 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 siq2 0 1 select iq phase to i channel phase to q channel siq2 0 1 select iq gain to i channel gain to q channel default = 10 default = 2 default = 10 01975-p r g-038 f i g u re 38. not e : 1. t h is regis t er i s not us ed under nor mal opera t ing c o nd itio ns. register 11afc register afc scaling coefficient control bits afc e n able m4 m5 m6 m7 m8 m9 m1 0 m1 1 m1 2 m1 3 m1 4 m1 5 m1 6 ae 1 m3 c2 (1 ) c1 (0 ) c3 (0 ) c4 (0 ) m1 m2 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 ae1 0 1 internal afc off on 01975-p r g-039 f i g u re 39. not e s : 1. s e e t h e in t e rn a l af c sec t i o n t o p r og r a m afc sca l i n g c o e f f i ci en t bit s . 2. t h e a f c s c a l ing c o ef f i cien t bits can be programmed us ing the f o l l owing f o rmul a: af c _ sc aling_c oef f i cient = round ((500 2 24 )/ xt a l )
adf7020 prelim inary technical data r e v. pr h | pa g e 38 o f 40 register 12test re gister counte r r eset digital test modes - ? test modes analog test mux image filter adjust osc test force ld high s o urce pr esc a l er pll test modes address bits sf6 sf5 t5 t6 t7 t8 sf1 sf2 sf3 sf4 t9 t4 t3 pr e c2 (0 ) c1 (0 ) c3 (1 ) c4 (1 ) t1 t2 qt1 cs 1 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 p 0 1 prescaler 4/5 (default) 8/9 cr1 0 1 counter reset default reset cs1 0 1 cal source internal serial if bw cal default = 32. increase number to increase bw if user cal on 01975-p r g-043 f i g u re 40. using the test dac on the a d f7020 to implement analog fm de mod an d me a s uring snr the t e st d a c al lo ws t h e o u t p u t o f t h e p o s t de mo d u l a t o r f i l t er for b o t h t h e l i ne ar an d c o r r el a t or / d e m o d u l a t ors ( f i g u r e 1 6 an d f i gur e 17) t o be view e d ext e r n al l y . i t tak e s t h e 1 6 -b i t f i l t er o u t p u t an d co n v er ts i t t o a high f r eq uen c y , sin g le-b i t o u t p u t usin g a s e cond- o r d er er r o r fe e d b a ck - ? con v er t e r . th e o u t p u t ca n be view e d on the x c lk ou t p i n. t h is signal , when if f i l t er e d a ppropr i a t el y , c a n t h e n b e u s e d to ? monitor the sig n als at t h e fs k / ask po st de mo dula to r filter output. this all o ws the de modulator output s n r to b e measured. eye di agra ms can al so be constructed of the receive d bit stre am to me asure t h e receive d sig n al quality. ? provid e analog fm d e m o d u lation . w h i l e t h e co r r ela t o r s and f i l t ers a r e clo c k e d b y d e m o d_clk, cd r_cl k clo c ks t h e t e st d a c. n o t e t h a t , a l t h oug h t h e t e st d a c f u n c t i o n s in a r e gu la r us er m o de , t h e best p e r f o r ma n c e is achie v e d w h en t h e cdr_cl k is in cr e a s e d u p t o o r a b o v e t h e f r e q u e nc y of de mod _ c l k . t h e c d r bl o c k d o e s not f u nc t i o n w h en t h is condi t io n exists. p r og ra mmin g t h e t e s t r e g i st er , reg i st er 12, enab les t h e t e s t d a c. b o t h t h e l i ne ar an d c o r r el ator / d e m o d u l ator output s c a n b e mu l t i p l e x e d i n t o t h e d a c . regist er 13 al lo ws a f i x e d o f fset t e r m t o b e r e m o v e d f r o m th e sig n al (t o r e m o v e t h e if com p on e n t i n t h e dd t cas e ). i t als o has a signal ga in t e r m t o al lo w th e usa g e o f th e m a xim u m d y nam i c ra n g e o f t h e d a c. s e tting up th e t e st d a c ? dig i tal t e s t m o des = 7: ena b les th e t e s t d a c, wi th n o o f fs et re mov a l . ? dig i tal t e s t m o des = 10: ena b les th e t e s t d a c, wi th o f fs et re mov a l . the o u t p u t o f t h e ac t i v e de mo d u l a t o r dr i v es t h e d a c, t h a t is, if t h e f s k c o r r el at or / d e m o d u l ator i s s e l e c t e d , t h e c o r r el a t or f i lte r o u t p u t dr i v es t h e d a c.
prelim inary technical data adf7020 r e v. pr h | pa g e 39 o f 40 register 13offset removal and sig n al gain regis t er kp ki control bits pulse extension test dac gain test dac offset removal pe1 pe2 pe3 pe4 c2 (0 ) c1 (1 ) c3 (1 ) c4 (1 ) db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 pe4 0 0 0 . . . 1 pe3 0 0 0 . . . 1 pe2 0 0 1 . . . 1 pulse extension normal pulse width 2 pulse width 3 pulse width . . . 16 pulse width pe1 0 1 0 . . . 1 01975-p r g-044 f i g u re 41. not e : 1. b e ca u s e t h e li n e a r dem o dula t o r s out p ut i s pr opor t i on a l t o fr eq uen c y , i t usu a lly c o n s i s t s of a n o f f s et c o m b i n ed wi t h a r e la t i v e ly l o w si g n a l . t h e o f f s et ca n be remov e d, up t o a maximum of 1.0 and gained t o us e the ful l d y namic range of the d a c : d a c _ input = (2^ t e st_d a c _ga i n ) ( signal ? t e st_d a c _ o f f set_r emo v al /4096)
adf7020 prelim inary technical data r e v. pr h | pa g e 40 o f 40 outline dimensions seating plane 1.50 1.45 1.40 coplanarity 0.05 0.05 max 0.02 nom 0.35 0.20 0.25 5.25 4.70 sq 2.25 0.50 bsc 5.50 bsc bo t t o m view pin 1 indicator top view 0.55 0.50 0.45 7.00 bsc sq 0.25 min 0.25 min 1 12 13 24 25 36 37 48 f i gure 42. 4 8 -l ead m i cro l e ad f r a m e chip s c a l e p a ckage [mlfcsp ] (c p - 4 8 m ) 7 mm 7 m m b o d y di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option ADF7020BCP ?40c to +85c 48-lead micro l e ad frame chip scale package [mlfcsp] cp-48m 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . pr0197506/04(p r h)

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